Datasheet

162
7734Q–AVR–02/12
AT90PWM81/161
13.10 PSCR Input Mode 2: Stop signal, Execute Opposite Dead-Time and Wait
Figure 13-17. PSCr behavior versus PSCr Input A in Fault Mode 2.
PSCR Input A is take into account during DT0 and OT0 only. It has no effect during DT1 and
OT1.
When PSCr Input A event occurs, PSCR releases PSCOUTr0, jumps and executes DT1 plus
OT1 and then waits for PSCR Input A inactive state.
Even if PSCR Input A is released during DT1 or OT1, DT1 plus OT1 sub-cycle is always com-
pletely executed.
Figure 13-18. PSCr behavior versus PSCr Input B in Fault Mode 2.
PSCR Input B is take into account during DT1 and OT1 only. It has no effect during DT0 and
OT0.
When PSCR Input B event occurs, PSCR releases PSCOUTr1, jumps and executes DT0 plus
OT0 and then waits for PSCR Input B inactive state.
Even if PSCR Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always com-
pletely executed.
PSCOUTn0
PSCOUTn1
PSC Input A
PSC Input B
DT0
OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1
PSCOUTn0
PSCOUTn1
PSC Input A
PSC Input B
DT0
OT0 DT1 OT1DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1