Datasheet

159
7734Q–AVR–02/12
AT90PWM81/161
Figure 13-13. Burst generation.
13.8.4 PSCR Input Configuration
The PSCR Input Configuration is done by programming bits in configuration registers.
13.8.4.1 Filter Enable
If the “Filter Enable” bit is set, a digital filter of four cycles is inserted before evaluation of the sig-
nal. The disable of this function is mainly needed for prescaled PSCR clock sources, where the
noise cancellation gives too high latency.
Important: If the digital filter is active, the level sensitivity is true also with a disturbed PSCR
clock to deactivate the outputs (emergency protection of external component). Likewise when
used as fault input, PSCr Input A or Input B have to go through PSCR to act on PSCOUTr0/1/2/3
output. This way needs that CLK
PSCR
is running. So thanks to PSCR Asynchronous Output Con-
trol bit (PAOCrA/B), PSCrIN0/1 input can deactivate directly the PSCR output. Notice that in this
case, input is still taken into account as usually by Input Module System as soon as CLK
PSCR
is
running.
Figure 13-14. PSCR input filtering.
13.8.4.2 Signal Polarity
One can select the active edge (edge modes) or the active level (level modes). See PELEV0x bit
description in Section “PFRC0A - PSCR Input A Control Register”, page 175.
If PELEV0x bit set, the significant edge of PSCr Input A or B is rising (edge modes) or the active
level is high (level modes) and vice versa for unset/falling/low.
OFF
PSCOUTn0
PSCOUTn1
PSCn Input A
(high level)
PSCn Input A
(low level)
BURST
Digital
Filter
4 x CLK
PSC Input
Module X
Ouput
Stage
PSCOUTnX
PIN
PSCn Input A or B
CLK
PSC
PSC