Datasheet

157
7734Q–AVR–02/12
AT90PWM81/161
Figure 13-9. PSCOUTr0 retriggered by PSCr Input A (edge retriggering).
Note: This example is given in “Input Mode 8” in “2 or 4 ramp mode”. See Figure 13-26 on page 166 for
details.
Figure 13-10. PSCOUTr0 retriggered by PSCr Input A (level acting).
Note: This example is given in “Input Mode 1” in “2 or 4 ramp mode”. See Figure 13-15 on page 161 for
details.
13.8.3 Retrigger PSCOUTr1 On External Event
PSCOUTr1 output can be reset before end of On-Time 1 on the change on PSCr Input B. The
polarity of PSCr Input B is configurable thanks to a sense control block. PSCr Input B can be
configured to do not act or to act on level or edge modes. PSCr Input B can be the Output of the
analog comparator or the PSCINr input.
On-Time 0 On-Time 1
PSCOUTn0
PSCOUTn1
Dead-Time 1
Dead-Time 0
PSCn Input A
(falling edge)
PSCn Input A
(rising edge)
On-Time 0 On-Time 1
PSCOUTn0
PSCOUTn1
Dead-Time 1
Dead-Time 0
PSCn Input A
(high level)
PSCn Input A
(low level)