Datasheet

156
7734Q–AVR–02/12
AT90PWM81/161
Figure 13-8. PSCR input module.
13.8.1 PSCR Retrigger Behavior versus PSCR running modes
In two ramp or four ramp mode, Retrigger Inputs A or B cause the end of the corresponding
cycle A or B and the beginning of the following cycle B or A.
In one ramp mode, Retrigger Inputs A or B reset the current PSCR counting to zero.
13.8.2 Retrigger PSCOUTr0 On External Event
PSCOUTr0 output can be reset before end of On-Time 0 on the change on PSCr Input A. PSCr
Input A can be configured to do not act or to act on level or edge modes. The polarity of PSCr
Input A is configurable thanks to a sense control block. PSCr Input A can be the Output of the
analog comparator or the PSCINr input.
As the period of the cycle decreases, the instantaneous frequency of the two outputs increases.
Digital
Filter
PFLTErA
(PFLTErB)
PAOCrA
(PAOCrB)
Input
Processing
(retriggering ...)
PSC Core
(Counter,
Waveform
Generator, ...)
Output
Control
1
0
PSCOUTr0
(PSCOUTr1)
CLK
PSC
CLK
PSC
CLK
PSC
PELEVrA /
(PELEVrB)
PRFMrA3:0
(PRFMrB3:0)
PCAErA
(PCAErB)
2
4
AC1O: Analog
Comparator
Output
PSCINr
PISELrA0
(PISELrB0)
0 0
0 1
PSCINrA
PISELrA1
(PISELrB1)
1 0
1 1
PSCINrB
PSCR Input A
(PSCR Input B)