Datasheet

148
7734Q–AVR–02/12
AT90PWM81/161
13.3 PSCR Description
Figure 13-1. Power Stage Controller block diagram.
The principle of the PSCR is based on the use of a counter (PSCR counter). This counter is
able to count up and count down from and to values stored in registers according to the selected
running mode.
The PSCR is seen as two symmetrical entities. One part named part A which generates the out-
put PSCOUTr0 and the second one named part B which generates the PSCOUTr1 output.
Each part A or B has its own PSCR Input Module to manage selected input.
13.3.1 Output Polarity
The polarity “active high” or “active low” of the PSCR outputs is programmable. All the timing
diagrams in the following examples are given in the “active high” polarity.
DATABUS
OCRrRB
OCRrSB
OCRrRA
=
=
=
PSCR Counter
Waveform
Gererator B
PSC Input
Module B
PSC Input
Module A
PSCOUTr1
PCTLr PFRCrA PSOCr
OCRrSA
=
PCNFr PFRCrB
PICRr
Waveform
Gererator A
PSCOUTr0
Part B
Part A
PSCr Input B
PSCr Input A