Datasheet

145
7734Q–AVR–02/12
AT90PWM81/161
• Bit 0 – PEOPn: End Of PSC n Interrupt
This bit is set by hardware when PSC n achieves its whole cycle.
Must be cleared by software by writing a one to its location.
12.26.4 PSC Output Behavior During Reset
For external component safety reason, the state of PSC outputs during Reset can be pro-
grammed by fuses PSCRV, PSCRRB & PSC2RB.
These fuses are located in the Extended Fuse Byte:
Notes: 1. See Table 7-2 on page 53 for BODLEVEL Fuse decoding.
PSCRV gives the state low or high which will be forced on PSC outputs selected by PSC0RB &
PSC2RB fuses.
If PSCRV fuse equals 0 (programmed), the selected PSC outputs will be forced to low state. If
PSCRV fuse equals 1 (unprogrammed), the selected PSC outputs will be forced to high state.
If PSCRRB fuse equals 1 (unprogrammed), PSCOUTR0 & PSCOUTR1 keep a standard port
behavior. If PSC0RB fuse equals 0 (programmed), PSCOUTR0 & PSCOUTR1 are forced at
reset to low level or high level according to PSCRV fuse bit. In this second case, PSCOUTR0 &
PSCOUTR1 keep the forced state until PSOC0 register is written.
Table 12-22. PSC n ramp number description.
PRNn1 PRNn0 Description
0 0 The last event which has generated an interrupt occurred during ramp 1
0 1 The last event which has generated an interrupt occurred during ramp 2
1 0 The last event which has generated an interrupt occurred during ramp 3
1 1 The last event which has generated an interrupt occurred during ramp 4
Table 12-23. Extended Low Fuse byte.
Extended fuse byte Bit No Description Default value
PSC2RB 7 PSC2 reset behavior 1
PSC2RBA 6
PSC2 reset behavior for
OUT22 & 23
1
PSCRRB 5 PSC reduced reset behavior 1
PSCRV 4
PSCOUT & PSCOUTR reset
value
1
PSCINRB 3
PSC & PSCR inputs reset
behavior
1
BODLEVEL2
(1)
2
Brown-out detector trigger
level
1 (unprogrammed)
BODLEVEL1
(1)
1
Brown-out detector trigger
level
0 (programmed)
BODLEVEL0
(1)
0
Brown-out detector trigger
level
1 (unprogrammed)