Datasheet

142
7734Q–AVR–02/12
AT90PWM81/161
12.25.12 PICR2H and PICR2L - PSC 2 Input Capture Register
• Bit 7 – PCSTn: PSC Capture Software Trig bit
Set this bit to trigger off a capture of the PSC counter. When reading, if this bit is set it means
that the capture operation was triggered by PCSTn setting otherwise it means that the capture
operation was triggered by a PSC input.
The Input Capture is updated with the PSC counter value each time an event occurs on the
enabled PSC input pin (or optionally on the Analog Comparator output) if the capture function is
enabled (bit PCAEnx in PFRCnx register is set).
The Input Capture Register is 12-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit or
12-bit registers.
12.26 PSC2 Specific Register
12.26.1 POM2 - PSC 2 Output Matrix
0100b
“PSC Input Mode 4: Deactivate outputs without changing timing”, page 124
0101b
“PSC Input Mode 5: Stop signal and Insert Dead-Time”, page 124
0110b
“PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait”,
page 125
0111b
“PSC Input Mode 7: Halt PSC and Wait for Software Action”, page 125
1000b
“PSC Input Mode 8: Edge Retrigger PSC”, page 126
1001b
“PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC”, page 127
1010b
Reserved (do not use)
1011b
1100b
1101b
1110b
“PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Deactivate
Output”, page 128
1111b
Reserved (do not use)
Table 12-21. Level sensitivity and Fault Mode operation. (Continued)
PRFMnx3:0 Description
Bit 76543210
PCST2–––PICR2[11:8] PICR2H
PICR2[7:0] PICR2L
Read/Write RRRRRRRR
Initial Value00000000
Bit 7 6543210
POMV2B3 POMV2B2 POMV2B1 POMV2B0 POMV2A3 POMV2A2 POMV2A1 POMV2A0 POM2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0