Datasheet

139
7734Q–AVR–02/12
AT90PWM81/161
• Bit 2– PELEVnB1: PSC n Input Select for part B
Together with PELEVnB0, defines active edge or level on PSC part B.
• Bit 1– PISELnA1: PSC n Input Select for part A
Together with PISELnA0, defines active signal on PSC part A.
• Bit 0– PISELnB1: PSC n Input Select for part B
Together with PISELnB0, defines active signal on PSC part B.
12.25.8 PASDLYn - Analog Synchronization Delay Register
The Analog Synchronization Delay Register store an 8 bit delay used:
• For the input signal blanking. See Section “PSC Inputs”, page 114
• For shifting the PSCOUTnx edges and the PSCnASY signal. See Section “Analog
Synchronization”, page 131
Table 12-17. PSC edge & level input selection.
PELEVnB1 PELEVnB0 Description
00
The falling edge or low level of selected input generates the
significative event for retrigger or fault function
01
The rising edge or high level of selected input generates the
significative event for retrigger or fault function
10
The toggle of selected input generates the significative event for
retrigger or fault function
11Reserved
Table 12-18. PSC trigger & fault input selection.
PISELnA1 PISELnA0 Description
0 0 PSCINn
0 1 First analog comparator output
1 0 PSCINnA
1 1 Second analog comparator output
Table 12-19. PSC trigger & fault input selection.
PISELnB1 PISELnB0 Description
0 0 PSCINn
0 1 First analog comparator output
1 0 PSCINnA
1 1 Second analog comparator output
Bit 76543210
PASD LYn [7:0 ] PASD LYn
Read/Write WWWWWWWW
Initial Value00000000