Datasheet

138
7734Q–AVR–02/12
AT90PWM81/161
• Bit 4- PBFMn1: Balance Flank Width Modulation, bit 1
Defines the Flank Width Modulation, together with PBFMn0 bit in PCTLn register.
Note: 1. In one ramp mode, changing SA or SA+BSB also affect On-Time; see Figure 12-8 on page
108.
• Bit 3– PELEVnA1: PSC n Input Select for part A
Together with PELEVnA0, defines active edge or level on PSC part A.
Table 12-14. Analog signal synchronization or Input Blanking mode selection.
PASDLKn2 PASDLKn1 PASDLKn0 Description
000No Analog signal synchronization delay, no Input Blanking
001
No Analog signal synchronization delay, Input Blanking using PSC clock,
started on PSC end of cycle
010
No Analog signal synchronization delay, Input Blanking using PSC clock,
started on OCR SA event
011
No Analog signal synchronization delay, Input Blanking using PSC clock,
started on OCR SB event
100Analog signal synchronization delay with PSC clock, no Input Blanking
101Analog signal synchronization delay with PSC clock /2, no Input Blanking
110Analog signal synchronization delay with PSC clock /4, no Input Blanking
111Analog signal synchronization delay with PSC clock /8, no Input Blanking
Table 12-15. Flank Width Mode selection.
PBFMn1 PBFMn0 Description
0 0 Flank Width Modulation operates on RB (On-Time 1 only)
01
Flank Width Modulation operates on RB + RA (On-Time 0 and On-
Time 1)
1 0 Flank Width Modulation operates on SB (Dead-Time 1 only)
(1)
11
Flank Width Modulation operates on SB +SA (Dead-Time 0 and
Dead-Time 1)
Table 12-16. PSC edge & level input selection.
PELEVnA1 PELEVnA0 Description
00
The falling edge or low level of selected input generates the
significative event for retrigger or fault function
01
The rising edge or high level of selected input generates the
significative event for retrigger or fault function
10
The toggle of selected input generates the significative event for
retrigger or fault function
11Reserved