Datasheet

137
7734Q–AVR–02/12
AT90PWM81/161
• Bit 5 – PLOCKn: PSC n Lock
When this bit is set, the Output Compare Registers RA, RB, SA, SB, the Output Matrix POM2
and the PSC Output Configuration PSOCn can be written without disturbing the PSC cycles.
The update of the PSC internal registers will be done if the LOCK bit is released to zero.
• Bit 4:3 – PMODEn1: 0: PSC n Mode
Select the mode of PSC.
• Bit 2 – POPn: PSC n Output Polarity
If this bit is cleared, the PSC outputs are active Low.
If this bit is set, the PSC outputs are active High.
• Bit 1 – PCLKSELn: PSC n Input Clock Select
This bit is used to select between CLKPF or CLKPS clocks.
Set this bit to select the fast clock input (CLKPF).
Clear this bit to select the slow clock input (CLKPS).
• Bit 0 – POME2: PSC 2 Output Matrix Enable (PSC2 only)
Set this bit to enable the Output Matrix feature on PSC2 outputs. See “PSC2 Outputs” on page
129.
When Output Matrix is used, the PSC n Output Polarity POPn has no action on the outputs.
12.25.7 PCNFE2 - PSC 2 Extended Configuration Register
The PSC n Extended Configuration Register is used to configure the running mode of the PSC.
• Bit 7, 6, 5– PASDLKn(2:0): Analog Synchronization Output Delay or Input Blanking
select
Defines the modes for Analog signal synchronization delay or Input Blanking.
Table 12-13. PSC n mode selection.
PMODEn1 PMODEn0 Description
0 0 One Ramp mode
01Two Ramp mode
1 0 Four Ramp mode
1 1 Center Aligned mode
Bit 7 6543210
PASDLKn2 PASDLKn1 PASDLKn0 PBFMn1 PELEVnA1 PELEVnB1 PISELnA1 PISELnB1 PCNFE2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000