Datasheet

135
7734Q–AVR–02/12
AT90PWM81/161
• Bit 3 – POEN2D: PSCOUT23 Output Enable (PSC2 only)
When this bit is clear, second I/O pin affected to PSCOUT23 acts as a standard port.
When this bit is set, second I/O pin affected to PSCOUT23 is connected to the PSC waveform
generator B output and is set and clear according to the PSC operation.
• Bit 2 – POENnB: PSC n OUT Part B Output Enable
When this bit is clear, I/O pin affected to PSCOUTn1 acts as a standard port.
When this bit is set, I/O pin affected to PSCOUTn1 is connected to the PSC waveform generator
B output and is set and clear according to the PSC operation.
• Bit 1 – POEN2C: PSCOUT22 Output Enable (PSC2 only)
When this bit is clear, second I/O pin affected to PSCOUT22 acts as a standard port.
When this bit is set, second I/O pin affected to PSCOUT22 is connected to the PSC waveform
generator A output and is set and clear according to the PSC operation.
• Bit 0 – POENnA: PSC n OUT Part A Output Enable
When this bit is clear, I/O pin affected to PSCOUTn0 acts as a standard port.
When this bit is set, I/O pin affected to PSCOUTn0 is connected to the PSC waveform generator
A output and is set and clear according to the PSC operation.
12.25.2 OCRnSAH and OCRnSAL - Output Compare SA Register
12.25.3 OCRnRAH and OCRnRAL - Output Compare RA Register
Table 12-12. Synchronization source description in centered mode.
PSYNCn1 PSYNCn0 Description
00
Send signal on match with OCRnRA (during counting down of PSC)
The minimum value of OCRnRA must be 1
01
Send signal on match with OCRnRA (during counting up of PSC)
The minimum value of OCRnRA must be 1
1 0 No synchronization signal
1 1 No synchronization signal
Bit 76543210
––––OCRnSA[11:8] OCRnSAH
OCRnSA[7:0] OCRnSAL
Read/Write WWWWWWWW
Initial Value00000000
Bit 76543210
––––OCRnRA[11:8] OCRnRAH
OCRnRA[7:0] OCRnRAL
Read/Write WWWWWWWW
Initial Value00000000