Datasheet

134
7734Q–AVR–02/12
AT90PWM81/161
12.24 Interrupts
This section describes the specifics of the interrupt handling as performed in AT90PWM81/161.
12.24.1 List of Interrupt Vector
Each PSC provides three interrupt vectors
• PSCn EC (End of Cycle): When enabled and when a match with OCRnRB occurs
• PSCn EEC (End of Enhanced Cycle): When enabled and when a match with OCRnRB
occurs at the 15
th
enhanced cycle
• PSCn CAPT (Capture Event): When enabled and one of the two following events occurs:
retrigger, capture of the PSC counter or Synchro Error.
See “PIM2 - PSC2 Interrupt Mask Register” on page 143.
12.25 PSC Register Definition
Registers are explained for PSC0. They are identical for PSC1. For PSC2 only different registers
are described.
12.25.1 PSOC2 - PSC 2 Synchro and Output Configuration
• Bit 7 – POS23: PSCOUT23 Selection (PSC2 only)
When this bit is clear, PSCOUT23 outputs the waveform generated by Waveform Generator B.
When this bit is set, PSCOUT23 outputs the waveform generated by Waveform Generator A.
• Bit 6 – POS22: PSCOUT22 Selection (PSC2 only)
When this bit is clear, PSCOUT22 outputs the waveform generated by Waveform Generator A.
When this bit is set, PSCOUT22 outputs the waveform generated by Waveform Generator B.
• Bit 5:4 – PSYNCn1:0: Synchronization Out for ADC Selection
Select the polarity and signal source for generating a signal which will be sent to the ADC for
synchronization.
Bit 7 6543210
POS23 POS22 PSYNC21 PSYNC20 POEN2D POEN2B POEN2C POEN2A PSOC2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 12-11. Synchronization source description in one/two/four ramp modes.
PSYNCn1 PSYNCn0 Description
0 0 Send signal on leading edge of PSCOUTn0 (match with OCRnSA)
01
Send signal on trailing edge of PSCOUTn0 (match with OCRnRA or
fault/retrigger on part A)
1 0 Send signal on leading edge of PSCOUTn1 (match with OCRnSB)
11
Send signal on trailing edge of PSCOUTn1 (match with OCRnRB or
fault/retrigger on part B)