Datasheet

133

7734Q–AVR–02/12

AT90PWM81/161

A PSC which receive its Run signal from the previous PSC transmits its fault signal (if enabled)

to this previous PSC. So a slave PSC propagates its fault events when they are configured and

enabled.

12.23 PSC Clock Sources

PSC must be able to generate high frequency with enhanced resolution.

Each PSC has two clock inputs:

• CLK PLL from the PLL

•CLK I/O

Figure 12-42. Clock selection.

PCLKSELn bit in PSC n Configuration register (PCNFn) is used to select the clock source.

PPREn1/0 bits in PSC n Control Register (PCTLn) are used to select the divide factor of the

clock.

Table 12-10. Output Clock versus selection and prescaler.

PCLKSELn PPREn1 PPREn0 CLKPSCn output

000CLK I/O

0 0 1 CLK I/O / 4

0 1 0 CLK I/O / 32

0 1 1 CLK I/O / 256

100CLK PLL

1 0 1 CLK PLL / 4

1 1 0 CLK PLL / 32

1 1 1 CLK PLL / 256

CLK

PSCn

CLK

PLL

I/O

CK/4

CK/32

CK/256

PRESCALER

PPREn1/0

PCLKSELn