Datasheet

132
7734Q–AVR–02/12
AT90PWM81/161
12.22 PSC Synchronization
Note: In AT90PWM81/161, this feature is not relevant and PRUN2, PARUN2 are stuck at zero.
2 or 3 PSC can be synchronized together. In this case, two waveform alignments are possible:
• The waveforms are center aligned in the Center Aligned mode if master and slaves are all
with the same PSC period (which is the natural use).
• The waveforms are edge aligned in the 1, 2 or 4 ramp mode
Figure 12-41. PSC run synchronization.
If the PSCm has its PARUNn bit set, then it can start at the same time than PSCn-1.
PRUNn and PARUNn bits are located in PCTLn register. See “PCTL2 - PSC 2 Control Register”
on page 140.
Note: Do not set the PARUNn bits on the three PSC at the same time.
Thanks to this feature, we can for example configure two PSC in slave mode (PARUNn = 1 /
PRUNn = 0) and one PSC in master mode (PARUNm = 0 / PRUNm = 0). This PSC master can
start all PSC at the same moment (PRUNm = 1).
12.22.1 Fault events in Autorun mode
To complete this master/slave mechanism, fault event (input mode 7) is propagated from PSCn-
1 to PSCn and from PSCn to PSCn-1.
A PSC which propagate a Run signal to the following PSC stops this PSC when the Run signal
is deactivate.
According to the architecture of the PSC synchronization which build a “daisy-chain on the PSC
run signal” between the three PSC, only the fault event (mode 7) which is able to “stop” the PSC
through the PRUN bits is transmitted along this daisy-chain.
PA RU N0
PRUN0
Run PSC0
PSC0
PA RU N1
PRUN1
Run PSC1
PSC1
PA RU N2
PRUN2
Run PSC2
PSC2
SY0Out
SY0In
SY1In
SY2In
SY1Out
SY2Out