Datasheet

131
7734Q–AVR–02/12
AT90PWM81/161
12.20 Analog Synchronization
PSC generates a signal to synchronize the sample and hold or the ADC start; synchronization is
mandatory for measurements.
This signal can be selected between all falling or rising edge of PSCn0 or PSCn1 outputs as
defined per Table 12-11 on page 134 and Table 12-12 on page 135.
The signal can be shifted by a digital delay defined by the register PASDLY. The shifting clock
can be either Clkpsc or Clkpsc/4, as described per Bit 7, 6, 5– PASDLKn(2:0): Analog Synchro-
nization Output Delay or Input Blanking select on page 137.
Figure 12-40. Analog synchronization.
12.21 Interrupt Handling
As each PSC can be dedicated for one function, each PSC has its own interrupt system.
List of interrupt sources:
• Counter reload (end of On Time 1)
• End of Enhanced Cycle
• PSC Input event (active edge or at the beginning of level configured event)
• PSC Mutual Synchronization Error
00 01 10 11
CLKPSCn/4
CLKPSCn
PASDLKn(2)
PSCnASY
Digital
Delay
PASDLYn
PSYNCn(1:0)
OCRnSA
match
OCRnRA
match
A Trig/Fault
OCRnSB
match
OCRnRB
match
B Trig/Fault
CLKPSCn/2
CLKPSCn/8
PASDLKn(2:0)
5
4
6
7
0
1