Datasheet

119
7734Q–AVR–02/12
AT90PWM81/161
Figure 12-20. Burst generation.
12.8.4 PSC Input Configuration
The PSC Input Configuration is done by programming bits in configuration registers.
12.8.4.1 Filter Enable
If the “Filter Enable” bit is set, a digital filter of four cycles is inserted before evaluation of the sig-
nal. The disable of this function is mainly needed for prescaled PSC clock sources, where the
noise cancellation gives too high latency.
Important: If the digital filter is active, the level sensitivity is true also with a disturbed PSC clock
to deactivate the outputs (emergency protection of external component). Likewise when used as
fault input, PSCn Input A or Input B have to go through PSC to act on PSCOUTn0/1/2/3 output.
This way needs that CLK
PSC
is running. So thanks to PSC Asynchronous Output Control bit
(PAOCnA/B), PSCnIN0/1 input can deactivate directly the PSC output. Notice that in this case,
input is still taken into account as usually by Input Module System as soon as CLK
PSC
is running.
Figure 12-21. PSC input filtering.
12.8.4.2 Signal Polarity
One can select the active edge (edge modes) or the active level (level modes). See PELEVnx bit
description in “PFRCnA - PSC n Input A Control Register” on page 141.
If PELEVnx bit set, the significant edge of PSCn Input A or B is rising (edge modes) or the active
level is high (level modes) and vice versa for unset/falling/low.
OFF
PSCOUTn0
PSCOUTn1
PSCn Input A
(high level)
PSCn Input A
(low level)
BURST
Digital
Filter
4 x CLK
PSC Input
Module X
Ouput
Stage
PSCOUTnX
PIN
PSCn Input A or B
CLK
PSC
PSC