Datasheet

117
7734Q–AVR–02/12
AT90PWM81/161
Figure 12-16. PSCOUTn0 retrograde by PSCn Input A (edge retriggering).
Note: This example is given in “Input Mode 8” in “2 or 4 ramp mode”. See Figure 12-33 on page 126 for
details.
Figure 12-17. PSCOUTn0 retriggered by PSCn Input A (level acting).
Note: This example is given in “Input Mode 1” in “2 or 4 ramp mode”. See Figure 12-22 on page 121 for
details.
12.8.3 Retrigger PSCOUTn1 On External Event
PSCOUTn1 output can be reset before end of On-Time 1 on the change on PSCn Input B. The
polarity of PSCn Input B is configurable thanks to a sense control block. PSCn Input B can be
configured to do not act or to act on level or edge modes. PSCn Input B can be the Output of the
analog comparator or the PSCINn input.
As the period of the cycle decreases, the instantaneous frequency of the two outputs increases.
On-Time 0 On-Time 1
PSCOUTn0
PSCOUTn1
Dead-Time 1
Dead-Time 0
PSCn Input A
(falling edge)
PSCn Input A
(rising edge)
On-Time 0 On-Time 1
PSCOUTn0
PSCOUTn1
Dead-Time 1
Dead-Time 0
PSCn Input A
(high level)
PSCn Input A
(low level)