Datasheet

116
7734Q–AVR–02/12
AT90PWM81/161
Figure 12-15. PSC input module B.
12.8.1 PSC Retrigger Behavior versus PSC running modes
In centered mode, Retrigger Inputs have no effect.
In two ramp or four ramp mode, Retrigger Inputs A or B cause the end of the corresponding
cycle A or B and the beginning of the following cycle B or A.
In one ramp mode, Retrigger Inputs A or B reset the current PSC counting to zero.
12.8.2 Retrigger PSCOUTn0 On External Event
PSCOUTn0 output can be reset before end of On-Time 0 on the change on PSCn Input A.
PSCn Input A can be configured to do not act or to act on level or edge modes. The polarity of
PSCn Input A is configurable thanks to a sense control block. PSCn Input A can be the Output of
the analog comparator or the PSCINn input.
As the period of the cycle decreases, the instantaneous frequency of the two outputs increases.
AC2O: Analog
Comparator
Output
PSCINn
Digital
Filter
PISELnB0
PFLTEnB
PAOCnB
Input
Processing
(retriggering ...)
PSC Core
(Counter,
Waveform
Generator, ...)
Output
Control
1
0
0 0
0 1
PSCOUTn0
(PSCOUTn1)
(PSCOUT22)
(PSCOUT23)
CLK
PSC
CLK
PSC
CLK
PSC
PELEVnB
PRFMnB3:0
PCAEnB
4
AC3O:Analog
Comparator
Output
PSCINnA
PISELnB1
1 0
1 1
PSC n Input B