Datasheet

115
7734Q–AVR–02/12
AT90PWM81/161
According to PSC n Input A Control Register (see “PFRCnA - PSC n Input A Control Register”
on page 141), PSC n input A can act as a Retrigger or Fault input.
Each part A or B can be triggered by up to four signals as defined per Table 12-18 on page 139
and Table 12-19 on page 139.
Part A of PSC has also a blanking module allowing to cancel unwanted transitions which may
appear on the PSC n input A during a certain period of time.
The blanking start is defined by the bits PASDLKn(2:0) as per Table 12-14 on page 138.
The blanking duration is defined by the register PASDLYn. If the blanking is selected by the cor-
responding PASDLKn(2:0) bit, all transitions which may appears from the blanking start until a
time period are ignored.
Blanking is level sensitive, that is, a pulse started in the blanking window and still at active level
after the window will generate a valid retriggering event.
Figure 12-14. PSC input module A.
PSC input module B is shown on Table 12-15 on page 116.
According to PSC n Input B Control Register (see “PFRCnB - PSC n Input B Control Register”
on page 141), PSC n input B can act as a Retrigger or Fault input.
AC2O: Analog
Comparator
Output
PSCINn
Digital
Filter
PISELnA0
PFLTEnA
PAOCnA
Input
Processing
(retriggering ...)
PSC Core
(Counter,
Waveform
Generator, ...)
Output
Control
1
0
0 0
0 1
PSCOUTn0
(PSCOUTn1)
(PSCOUT22)
(PSCOUT23)
CLK
PSC
CLK
PSC
PELEVnA /
PRFMnA3:0
PCAEnA
4
AC3O: Analog
Comparator
Output
PSCINnA
PISELnA1
1 0
1 1
PSC n Input A
Input
Blanking
PASDLY
OCR SB
3
PSC start
cycle
OSR SA
PASDLKn(2:0)
2
1
Blanking Start
=0, 4..7
No Blanking