Datasheet

103
7734Q–AVR–02/12
AT90PWM81/161
12.4 Signal Description
Figure 12-3. PSC external block view.
Note: 1. available only for PSC2.
2. n = 0, 1 or 2.
12.4.1 Input Description
Table 12-1. Internal inputs.
Note: 1. See Figure 12-41 on page 132
OCRnRB[11:0]
OCRnRA[11:0]
OCRnSA[11:0]
OCRnRB[15:12]
OCRnSB[11:0]
PICRn[11:0]
IRQ PSCn
SYnIn
PSCINn
Analog
Comparator
n Output
PSCOUTn0
PSCOUTn2
SYnOut
CLK
4
12
12
12
12
CLK
PSCOUTn1
PSCOUTn3
12
PSCnASY
StopOut
StopIn
I/O
PLL
(1)
(1)
(Flank Width
Modulation)
2
2
Name Description Type width
OCRnRB[11:0] Compare value which reset signal on Part B (PSCOUTn1) Register 12 bits
OCRnSB[11:0] Compare value which set signal on Part B (PSCOUTn1) Register 12 bits
OCRnRA[11:0] Compare value which reset signal on Part A (PSCOUTn0) Register 12 bits
OCRnSA[11:0] Compare value which set signal on Part A (PSCOUTn0) Register 12 bits
OCRnRB[15:12]
Frequency resolution enhancement value (flank width
modulation)
Register 4 bits
CLK I/O Clock input from I/O clock Signal
CLK PLL Clock input from PLL Signal
SYnIn Synchronization in (from adjacent PSC)
(1)
Signal
StopIn Stop input (for synchronized mode) Signal