Datasheet

101
7734Q–AVR–02/12
AT90PWM81/161
12.3 PSC Description
Figure 12-1. Power Stage Controller 0 or 1 block diagram.
Note: n = 0, 1.
The principle of the PSC is based on the use of a counter (PSC counter). This counter is able to
count up and count down from and to values stored in registers according to the selected run-
ning mode.
The PSC is seen as two symmetrical entities. One part named part A which generates the output
PSCOUTn0 and the second one named part B which generates the PSCOUTn1 output.
Each part A or B has its own PSC Input Module to manage selected input.
DATABUS
OCRnRB
OCRnSB
OCRnRA
=
=
=
PSC Counter
Waveform
Generator B
PSC Input
Module B
PSC Input
Module A
PSCOUTn1
PCTLn PFRCnA PSOCn
OCRnSA
=
PCNFn PFRCnB
PICRn
Waveform
Generator A
PSCOUTn0
Par t B
Par t A
PSCn I n p ut B
PSCn I n p ut A
PCNFEn PASDLYn