Features • High performance, low power Atmel®AVR® 8-bit Microcontroller • Advanced RISC architecture • • • • – 131 powerful instructions - most single clock cycle execution – 32 × 8 general purpose working registers – Fully static operation – Up to 1 MIPS throughput per MHz – On-chip 2-cycle multiplier Data and non-volatile program memory – 8/16Kbytes of in-system programmable program memory flash • Endurance: 10,000 write/erase cycles • Lock bits protection • Optional 2/4Kbytes boot code section with i
AT90PWM81/161 – Power-on reset and programmable brown-out detection – Flag array in bit-programmable I/O space (three bytes) – In-system programmable via SPI port – Internal low power calibrated RC oscillator (8MHz or 1MHz, low jitter) – On chip PLL for fast PWM (32MHz, 48MHz, 64MHz) and CPU (12MHz, 16MHz); PLL source RC & XTAL – Dynamic clock switch – Temperature sensor • Operating voltage: 2.7V - 5.
AT90PWM81/161 2. Pin Configurations Figure 2-1. 20-pin packages.
NC (PSCINr/ACMP1M/XTAL2) PE2 (PSCOUTR0/PSCINrB) PD1 (ADC0/ACMP1) PD2 (ADC1/ACMP2_OUT) PD3 (ADC2/ACMP2M/PSCOUTR1) PB3 (ADC3/ACMPM/MOSI) PB4 NC 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 AT90PWM81/161 QFN 32 5*5 NC (ACMP3_OUT_A/SS/CLKO) PD0 (PSCOUT20) PB1 (INT0/PSCOUT21) PB2 VCC GND (ACPM1_OUT/PSCIN2/XTAL1) PE1 NC 7734Q–AVR–02/12 PB7 (ADC9/PSCOUT22/ICP1) PD7 (ADC10/PSCINrA) PB6 (ADC8/MISO/ACMP3) PD6 (AMP0+) NC PB0 (PSCOUT23/T1/ACMP3_OUT) PE0 (RESET/OCD/INT2) Figure 2-2.
AT90PWM81/161 Table 2-1. Functions description. MNEMONIC NAME, FUNCTION & ALTERNATE FUNCTION GND Ground: 0V reference AGND Analog Ground: 0V reference for analog part VCC Power Supply AVCC Analog Power Supply: This is the power supply voltage for analog part For a normal use this pin must be connected. AREF Analog Reference: Reference for analog converter. This is the reference voltage of the A/D converter.
AT90PWM81/161 Table 2-2. Port PB0 PE0 PD0 PB1 PB2 VCC GND PE1 PE2 Pin out description. SO 20 QFN32 pins pins GP 1 30 T1 2 31 RESET# OCD, INT2 NA 2 CLKO, SS 3 3 4 4 INT0 5 5 Power Supply 6 6 Ground 7 7 XTAL1 8 10 XTAL2 PD1 9 PD2 10 PD3 NA PB3 11 PB4 12 PD4 NA PB5 13 AVCC 14 AGND 15 16 PD5 17 PD6 18 PB6 19 PD7 NA PB7 20 2.1 2.1.
AT90PWM81/161 2.1.4 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.
AT90PWM81/161 3. AVR CPU Core 3.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 3.2 Architectural Overview Figure 3-1. Block diagram of the AVR architecture.
AT90PWM81/161 The fast-access Register File contains 32 × 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
AT90PWM81/161 3.4 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the “Instruction Set Summary” on page 301. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
AT90PWM81/161 • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Summary” on page 301 for detailed information. 3.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
AT90PWM81/161 Figure 3-3. The X-register, Y-register, and Z-register. 15 X-register XH XL 7 0 R27 (0x1B) YH YL 7 0 R29 (0x1D) Z-register 0 R26 (0x1A) 15 Y-register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 ZL 7 R31 (0x1F) 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see “Instruction Set Summary” on page 301 for details). 3.
AT90PWM81/161 Figure 3-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 3-4. The parallel instruction fetches and instruction executions.
AT90PWM81/161 programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 233. 3.8.1 Interrupt Behavior When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.
AT90PWM81/161 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly code example sei ; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C code example _SEI(); /* set Global Interrupt Enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ 3.8.
AT90PWM81/161 4. Memories This section describes the different memories in the Atmel AT90PWM81/161. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the AT90PWM81/161 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 4.1 In-System Reprogrammable Flash Program Memory The AT90PWM81/161 contains 8/16Kbytes On-chip In-System Reprogrammable Flash memory for program storage.
AT90PWM81/161 4.2 SRAM Data Memory Figure 4-2 shows how the Atmel AT90PWM81/161 SRAM memory is organized. The AT90PWM81/161 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
AT90PWM81/161 Figure 4-3. On-chip data SRAM access cycles. T1 T2 T3 clkCPU Address Compute Address Address valid Write Data WR Read Data RD Memory Access Instruction 4.3 Next Instruction EEPROM Data Memory The AT90PWM81/161 contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles.
AT90PWM81/161 4.3.2 EEARH and EEARL - EEPROM Address Registers Bit Read/Write Initial Value 15 14 13 12 11 10 9 – – – – – – – 8 EEAR8 EEARH EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 7 6 5 4 3 2 1 0 R/W R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 X X X X X X X X X • Bits 15..9 – Reserved Bits These bits are reserved bits in the AT90PWM81/161 and will always read as zero. • Bits 8..0 – EEAR8..
AT90PWM81/161 • Bits 5..4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEWE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 4-1. While EEWE is set, any write to EEPMn will be ignored.
AT90PWM81/161 Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware.
AT90PWM81/161 The order the different bits and registers should be accessed is: 1 Write EEPAGE in EECR (loading of temporary EEPROM buffer is enabled). 2 Write the address bits needed to address bytes within a page into EEARL. 3 Write data to EEDR. 4 Repeat 2 and 3 above until the buffer is filled up or until all data is loaded. 5 Write the remaining address bits into EEARH:EEARL. a. Select which programming mode that should be executed (EEPMn bits).
AT90PWM81/161 Table 4-4. Fuse high byte.
AT90PWM81/161 4.4.1 Code examples The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (for example, by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
AT90PWM81/161 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
AT90PWM81/161 4.5 I/O Memory The I/O space definition of the AT90PWM81/161 is shown in “Register Summary” on page 297. All AT90PWM81/161 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
AT90PWM81/161 5. System Clock and Clock Options The Atmel AT90PWM81/161 provides a large number of clock sources. Those can be divided in two categories: internal and external. After reset, CKSEL fuses select one clock source. Once the device is running, software clock switching is available on any other clock sources. Some hardware controls are provided for clock switching management but some specific procedures must be observed.
AT90PWM81/161 Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations. 5.1.2 clkI/O - I/O Clock The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. 5.1.
AT90PWM81/161 Device clocking options select (1) , PLL source and PE1 and PE2 functionality. (Continued) Table 5-1. Device clocking option CKSEL3..0 (3) CSEL3..0 (4) PE1 PE2 RC Osc (6) 1101 b XTAL1 XTAL2 Ext Osc (5) RC Osc (6) 1110 b XTAL1 XTAL2 (5) (6) 1111 b XTAL1 XTAL2 System clock PLL input (2) External crystal/ceramic resonator (3.0MHz - 8.0MHz) Ext Osc (5) External crystal/ceramic resonator (8.0MHz - 16.0MHz) External crystal/ceramic resonator (8.0MHz - 16.
AT90PWM81/161 The switch between 8MHz and 1MHz is done by the CKRC81 bit in MCUCR register. See “MCUCR - MCU Control Register” on page 42 for more details.The RC oscillator can be accessed by two CKSEL or CSEL configurations. At reset, the CKRC81 bit is initialised with the value compatible with CKSEL value (1 for CKSEL3..0 = 0110, 0 for all other values). The RC oscillator is active for any CKSEL3..0 or CSEL3..0 configuration where it is used as system clock or PLL source clock.
AT90PWM81/161 5.2.2.1 RC Oscillator calibration at Factory The RC oscillator is calibrated at 3V, 25°C for an 8MHz target frequency with an Accuracy ±1%. The corresponding value OSCAL (@Amb.) is stored in the signature row and automatically loaded in the OSCAL register at reset. The RC oscillator is monitored at 105°C or 125°C (versus Product version) with an accuracy within ±5% limits. 5.2.3 128KHz Internal Oscillator The 128kHz internal Oscillator is a low power Oscillator providing a clock of 128kHz.
AT90PWM81/161 The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by CKSEL3..1 fuses or by CSEL3..1 field as shown in Table 5-6. Table 5-6. Crystal oscillator operating modes. CKSEL3..1 (1) CSEL3..1 (2) Frequency range [MHz] Recommended range for capacitors C1 and C2 for use with crystals [pF] 100 (3) 0.4 - 0.9 – 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 - 16.0 12 - 22 Notes: 1. Flash fuse bits. 2.
AT90PWM81/161 5.2.5 External Clock To drive the device from this external clock source, CLKI should be driven as shown in Figure 53. To run the device on an external clock, the CKSEL Fuses or CSEL field must be programmed as shown in Table 5-1 on page 28. Figure 5-3. External clock drive configuration. External Clock Signal CLKI (XTAL1) GND When this clock source is selected, start-up times are determined by the SUT Fuses or CSUT field as shown in Table 5-8. Table 5-8.
AT90PWM81/161 The PLL is locked on the source oscillator which must remains close to 8MHz to assure proper lock of the PLL. Both internal RC Oscillator and PLL are switched off in Power-down and Standby sleep modes Table 5-9. Start-up times when the PLL is selected as system clock. CKSEL3..0 SUT1..0 Start-up time from powerdown Additional delay from reset (VCC = 5.
AT90PWM81/161 5.3 5.3.1 Dynamic Clock Switch Features AT90PWM81/161 provides a powerful dynamic clock switch that allows users to turn on and off clocks of the device on the fly. The built-in de-glitching circuitry allows clocks to be enabled or disabled asynchronously. This enables efficient power management schemes to be implemented easily and quickly. In a safety application, the dynamic clock switch circuit may continuously monitor the external clock fails.
AT90PWM81/161 Fuses substitution and clock source selection. CKSEL[3..0] CSEL[3..0] CSUT[1..0] COUT Default CLKSEL[3..0] SUT[1..0] CKOUT Reset R/W Reg. Register: CLKSELR Internal Data Bus Fuse: Fuse Low Byte ( ) SCLKRq * SEL Decodeur Figure 5-5. SEL-0 SEL-1 SEL-2 SEL-n Selected Configuration SUT[1..
AT90PWM81/161 5.3.6 1. Clock stability before switching Once the new clock source is selected, the count procedure is running. The user (code) should wait for the setting of the CLKRDY flag in CLKSCR register before to perform a switching. 2. Clock available on request AT any time, the user (code) can ask for the availability of a clock source. The user (code) can request it writing the appropriate command in the CLKSCR register. A full status on clock sources then can be done.
AT90PWM81/161 Here is a “light” C-code that describes such a sequence of commands.
AT90PWM81/161 5.4 5.4.1 System Clock Prescaler Features The AT90PWM81/161 system clock can be divided by setting the Clock Prescaler Register – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and clkFLASH are divided by a factor as shown in Table 5-10 on page 40. 5.4.
AT90PWM81/161 5.5.2 CLKPR – Clock Prescaler Register Bit 7 6 5 4 3 2 1 0 CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 Read/Write R/W R R R R/W R/W R/W R/W Initial Value 0 0 0 0 CLKPR See Bit Description • Bit 7 – CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero.
AT90PWM81/161 Table 5-10. 5.5.3 Clock prescaler select.
AT90PWM81/161 • Bit 1 – PLLE: PLL Enable When the PLLE is set, the PLL is started and if not yet started the internal RC Oscillator is started as PLL reference clock. If PLL is selected as a system clock source the value for this bit is always 1. • Bit 0 – PLOCK: PLL Lock Detector When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable CLKPLL for PSC. The time to lock is specified in Table 5-9 on page 34. 5.5.
AT90PWM81/161 the clock frequency and, of course, if the clock is alive. The user’s has itself to do the difference between ‘no_clock_signal’ and ‘clock_signal_not_yet_available’. • Bits 3:0 – CLKC3:0: Clock Control Bits 3 - 0 These bits define the command to provide to the ‘Clock Switch’ module. The special write procedure must be followed to change the CLKC bits (see “Bit 7 – CLKCCE: Clock Control Change Enable” on page 42). 1.
AT90PWM81/161 start-up times. In case of ‘Recover System Clock Source’ command, CSUT field is not affected (no recovering of SUT code). • Bits 3:0 – CSEL3:0: Clock Source Select CSEL bits are initialized with the values of CKSEL Fuse bits. In case of ‘Enable/Disable Clock Source’, ‘Request for Clock Availability’ or ‘Clock Source Switch’ command, CSEL field gets back the code of the clock source. Refer to Table 5-1 on page 28 and subdivisions of Section 5.2 ”Clock Sources” on page 28 for clock source codes.
AT90PWM81/161 6. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 6.1 Sleep Modes Figure 5-1 on page 27 presents the different clock systems in the AT90PWM81/161, and their distribution. The figure is helpful in selecting an appropriate sleep mode.
AT90PWM81/161 6.3 ADC Noise Reduction Mode When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the External Interrupts, Timer/Counter (if their clock source is external - T0 or T1) and the Watchdog to continue operating (if enabled). This sleep mode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the other clocks to run.
AT90PWM81/161 6.7 Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. 6.7.
AT90PWM81/161 be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section “I/O-Ports” on page 68 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to VCC/2, the input buffer will use excessive power.
AT90PWM81/161 6.8.2 PRR - Power Reduction Register Bit 7 6 5 4 3 2 1 0 PRPSC2 - PRPSCR PRTIM1 - PRSPI - PRADC Read/Write R/W R R/W R/W R R/W R R/W Initial Value 0 0 0 0 0 0 0 0 PRR • Bit 7 - PRPSC2: Power Reduction PSC2 Writing a logic one to this bit reduces the consumption of the PSC2 by stopping the clock to this module. When waking up the PSC2 again, the PSC2 should be re initialized to ensure proper operation.
AT90PWM81/161 7. System Control and Reset 7.1 7.1.1 System Control overview Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
AT90PWM81/161 Figure 7-1. Reset logic. DATA BUS PORF BORF EXTRF WDRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor Spike Filter RSTDIS Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] Table 7-1. Symbol VPOT Reset characteristics (1). Parameter Typical Maximum Units Power-on reset threshold voltage (rising) 1.4 2.3 V Power-on reset threshold voltage (falling) (2) 1.3 2.3 V 0.
AT90PWM81/161 Figure 7-2. MCU start-up, RESET tied to VCC. VCC RESET VPOT VRST tTOUT TIME-OUT INTERNAL RESET Figure 7-3. MCU start-up, RESET extended externally. VCC VPOT RESET TIME-OUT VRST tTOUT INTERNAL RESET 7.1.4 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 7-1 on page 51) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
AT90PWM81/161 7.1.5 Brown-out Detection AT90PWM81/161 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2. Table 7-2. BODLEVEL fuse coding (1)(2). BODLEVEL 2..
AT90PWM81/161 Figure 7-5. Brown-out reset during operation. VCC VBOT+ VBOT- RESET tTOUT TIME-OUT INTERNAL RESET 7.1.6 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 56 for details on operation of the Watchdog Timer. Figure 7-6. Watchdog reset during operation. CC CK 7.2 7.2.
AT90PWM81/161 • Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 1 – EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 0 – PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
AT90PWM81/161 user can avoid the four conditions above to ensure that the reference is turned off before entering Power-down mode. 7.3.2 Voltage Reference Characteristics Table 7-4. Symbol Parameter Condition Minimum Typical Maximum Units VBG Bandgap reference voltage 1.1 V tBG Bandgap reference start-up time 40 µs IBG Bandgap reference current consumption 15 µA Note: 7.4 Internal voltage reference characteristics (1). 1. Values are guidelines only.
AT90PWM81/161 In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the device from sleep-modes, and also as a general system timer. One example is to limit the maximum time allowed for certain operations, giving an interrupt when the operation has run longer than expected. In System Reset mode, the WDT gives a reset when the timer expires. This is typically used to prevent system hang-up in case of runaway code.
AT90PWM81/161 Assembly code example (1) WDT_off: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Clear WDRF in MCUSR in r16, MCUSR andi r16, (0xff & (0<
AT90PWM81/161 Assembly code example (1) WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence lds r16, WDTCSR ori r16, (1<
AT90PWM81/161 • Bit 6 - WDIE: Watchdog Interrupt Enable When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs. If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog Timer will set WDIF.
AT90PWM81/161 . Table 7-6. Watchdog timer prescaler select. WDP3 WDP2 WDP1 WDP0 Number of WDT oscillator cycles Typical time-out at VCC = 5.0V 0 0 0 0 2K (2048) cycles 16ms 0 0 0 1 4K (4096) cycles 32ms 0 0 1 0 8K (8192) cycles 64ms 0 0 1 1 16K (16384) cycles 0.125s 0 1 0 0 32K (32768) cycles 0.25s 0 1 0 1 64K (65536) cycles 0.5s 0 1 1 0 128K (131072) cycles 1.0s 0 1 1 1 256K (262144) cycles 2.0s 1 0 0 0 512K (524288) cycles 4.
AT90PWM81/161 8. Interrupts This section describes the specifics of the interrupt handling as performed in the Atmel AT90PWM81/161. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 13. 8.1 Interrupt Vectors in AT90PWM81/161 Table 8-1. Reset and interrupt vectors. Vector no.
AT90PWM81/161 the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 8-2. Reset and interrupt vectors placement in AT90PWM81/161 (1). BOOTRST IVSEL 1 Note: Reset address Interrupt vectors start address 0 0x000 0x001 1 1 0x000 Boot reset address + 0x001 0 0 Boot reset address 0x001 0 1 Boot reset address Boot reset address + 0x001 1. The Boot Reset Address is shown in Table 20-7 on page 246.
AT90PWM81/161 0x01C rjmp 0x01F rjmp ; 0x020RESET: ldi r16, high(RAMEND); Main program start 0x021 out SPH,r16 0x022 ldi r16, low(RAMEND) 0x023 0x024 out sei 0x025 ... SPL,r16 ; Enable interrupts ... ... ; Set Stack Pointer to top of RAM xxx ...
AT90PWM81/161 For AT90PWM161 .org 0x001 0x002 rjmp PSC2_CAPT ; PSC2 Capture event Handler 0x004 rjmp PSC2_EC ; PSC2 End Cycle Handler ... ... ... ; 0x03F rjmp SPM_RDY ; Store Program Memory Ready Handler ; .
AT90PWM81/161 8.1.2 MCUCR - MCU Control Register Bit 7 6 5 4 3 2 1 0 – – – PUD RSTDIS CKRC81 IVSEL IVCE Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash.
AT90PWM81/161 Assembly code example Move_interrupts: ; Enable change of Interrupt Vectors ldi r16, (1<
AT90PWM81/161 9. I/O-Ports 9.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
AT90PWM81/161 9.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 9-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 9-2. General digital I/O (1). PUD Q D DDxn Q CLR WDx RESET 1 Q Pxn D 0 PORTxn Q CLR WPx DATA BUS RDx RESET WRx RRx SLEEP SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O PUD: PULLUP DISABLE SLEEP: SLEEP CONTROL clkI/O : I/O CLOCK Note: 9.2.
AT90PWM81/161 If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 9.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 9.2.
AT90PWM81/161 Figure 9-3. Synchronization when reading an externally applied pin value. SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low.
AT90PWM81/161 Assembly code example (1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16, (1<
AT90PWM81/161 9.3 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 9-5 shows how the port pin control signals from the simplified Figure 9-2 on page 69 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 9-5. Alternate port functions (1).
AT90PWM81/161 Table 9-2. Generic description of overriding signals for alternate functions. Signal name Full name Description PUOE Pull-up override enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. PUOV Pull-up override value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.
AT90PWM81/161 • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 69 for more details about this feature. 9.3.2 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 9-3. Table 9-3. Port pin Port B pins alternate functions.
AT90PWM81/161 • ADC5/ACMP2/INT1/SCK – Bit 5 ADC5: Analog to Digital Converter, input channel 5. ACMP2: Analog Comparator 2 Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. INT1: External Interrupt source 1. This pin can serve as an external interrupt source to the MCU. SCK: Master Clock output, Slave Clock input pin for SPI channel.
AT90PWM81/161 Table 9-4 and Table 9-5 relates the alternate functions of Port B to the overriding signals shown in Figure 9-5 on page 73. Table 9-4. Overriding signals for alternate functions in PB7..PB4. Signal name PB7/PSCOUT22/ ICP1/ADC9 PB6/MISO/ ACMP3/ADC8 PB5/ADC5/ ACMP2/INT1/SCK PB4/MOSI/ADC3 /ACMPM PUOE 0 SPE.MSTR SPE.MSTR SPE.MSTR PUOV 0 PB6.PUD PB5.PUD PB4.PUD DDOE PSCen22 SPE.MSTR SPE.MSTR SPE.MSTR DDOV 1 0 0 0 PVOE PSCen22 SPE.MSTR SPE.MSTR SPE.
AT90PWM81/161 The alternate pin configuration is as follows: 9.3.3 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 9-6. Table 9-6. Port pin Port D pins alternate functions.
AT90PWM81/161 • ADC1/ACMP2_OUT, Bit 3 ADC1: Analog to Digital Converter, input channel 1. ACMP2_OUT: Analog Comparator 2 Output. • ADC0/ACMP1, Bit 2 ADC0: Analog to Digital Converter, input channel 0. ACMP1: Analog Comparator 1 Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. • PSCOUTR0/PSCINrB – Bit 1 PSCOUTR0: Output 0 of PSCR. PCSINrB: PSCR Second Alternate Digital Input.
AT90PWM81/161 Table 9-8. 9.3.4 Overriding signals for alternate functions in PD3..PD0. Signal name PD3/ADC1/ ACMP2_OUT PD2/ADC0/ ACMP1 PD1/PSCOUTR0/ PSCINrB PD0/ACMP3_OUT/SS/ CLKO PUOE 0 0 0 SPE.MSTR PUOV 0 0 0 PD0.PUD DDOE ACE2EN 0 PSCen00 ACMP3D|(SPE.
AT90PWM81/161 ACMP1M: Analog Comparator 1 Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. PCSINr: PSCR Digital Input. • XTAL1/PSCIN2/ACMP1_OUT – Bit 1 XTAL1: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated RC Oscillator. When used as a clock pin, the pin can not be used as an I/O pin. PCSIN2: PSC 2 Digital Input.
AT90PWM81/161 9.4.2 DDRB - Port B Data Direction Register Bit 9.4.3 7 6 5 4 3 2 1 0 DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0 PINB - Port B Input Pins Address Bit 9.4.
AT90PWM81/161 10. External Interrupts The External Interrupts are triggered by the INT2:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT2:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the External Interrupt Control Registers – EICRA (INT2:0).
AT90PWM81/161 Note: 10.0.2 1. n = 3, 2, 1 or 0. When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK register. Otherwise an interrupt can occur when the bits are changed. EIMSK - External Interrupt Mask Register Bit 7 6 5 4 3 2 1 - - - - - INT2 INT1 0 IINT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EIMSK • Bits 2..
AT90PWM81/161 11. Reduced 16-bit Timer/Counter1 The 16-bit Timer/Counter unit allows accurate program execution timing (event management). The main features are: • • • • • 11.1 Clear timer on compare match (auto reload) One input capture unit Input capture noise canceler External event counter Two independent interrupt sources (TOV1, ICF1) Overview Most register and bit references in this section are written in general form.
AT90PWM81/161 Figure 11-1. 16-bit timer/counter block diagram (1). Count Clear TOVn (Int.Req.) Control Logic clk Tn Clock Select Edge Detector TOP Tn BOTTOM (Ckio ) Timer/Counter TCNTn = =0 DATA BUS Fixed TOP Values ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnB Note: 11.1.1 AC1ICE 1. Refer to Table 2-1 on page 5 for Timer/Counter1 pin placement and description.
AT90PWM81/161 The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by the ICR1 Register, or by a set of fixed values. 11.1.2 Definitions The following definitions are used extensively throughout the section: 11.2 BOTTOM The counter reaches the BOTTOM when it becomes 0x0000. MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence.
AT90PWM81/161 Assembly code examples (1) ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... C code examples (1) unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into i */ i = TCNT1; ... Note: 1. The example code assumes that the part specific header file is included.
AT90PWM81/161 The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
AT90PWM81/161 The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
AT90PWM81/161 11.3.1 External Clock Source An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock (clkT1/clkT0). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 11-2 shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O).
AT90PWM81/161 Signal description (internal signals): Count Increment TCNT1 by 1. Clear Clear TCNT1 (set all bits to zero). clkT1 Timer/Counter clock. TOP Signalize that TCNT1 has reached maximum value. BOTTOM Signalize that TCNT1 has reached minimum value (zero). The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) containing the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight bits.
AT90PWM81/161 Figure 11-4. Input capture unit block diagram. DATA BUS (8-bit) TEMP (8-bit) ICRnH (8-bit) WRITE ICPnA ICRnL (8-bit) TCNTnH (8-bit) ICRn (16-bit Register) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Canceler Edge Detector ICFn (Int.Req.) When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), alternatively on the Analog Comparator output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered.
AT90PWM81/161 Both the Input Capture pin (ICP1) and the Analog Comparator 1 output (AC1O) inputs are sampled using the same technique as for the T1 pin (see Figure 11-2 on page 91). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles.
AT90PWM81/161 interrupt that automatically clears the TOV1 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the external events must not exceed the resolution of the counter.
AT90PWM81/161 Figure 11-6. Timer/counter timing diagram, no prescaling. clkI/O clkTn (clk I/O/1) TCNTn TOP - 1 TOP BOTTOM BOTTOM + 1 ICFn Figure 11-7 shows the count sequence close to MAX in various modes. Figure 11-7. Timer/counter timing diagram, no prescaling.
AT90PWM81/161 11.8 16-bit Timer/Counter Register Description 11.8.1 TCCR1B - Timer/Counter1 Control Register B Bit 7 6 5 4 3 2 1 0 ICNC1 ICES1 - WGM13 - CS12 CS11 CS10 Read/Write R/W R/W R R/W R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR1B • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture pin (ICP1) is filtered.
AT90PWM81/161 Table 11-2. Clock select bit description. (Continued) CS12 CS11 CS10 Description 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 External clock source on T1 pin. Clock on falling edge 1 1 1 External clock source on T1 pin. Clock on rising edge If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 11.8.
AT90PWM81/161 11.8.4 TIMSK1 - Timer/Counter1 Interrupt Mask Register Bit 7 6 5 4 3 2 1 – – ICIE1 – – – – 0 TOIE1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK1 • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the AT90PWM81/161, and will always read as zero.
AT90PWM81/161 12. Power Stage Controller – (PSCn) The Power Stage Controller is a high performance waveform controller. The Atmel AT90PWM81 includes one PSC2 block. 12.1 Features • • • • • • • • • • • • • 12.2 PWM waveform generation function (two complementary programmable outputs) Dead time control Standard mode up to 12 bit resolution Frequency and pulse width resolution enhancement mode (12 + 4 bits) Frequency up to 64Mhz Conditional waveform on external events (zero crossing, current sensing ...
AT90PWM81/161 12.3 PSC Description Figure 12-1. Power Stage Controller 0 or 1 block diagram. PSC Counter = Waveform Generator B PSCOUTn1 PSC Input Module B PSCn Input B OCRnRB DATABUS = OCRnSB Part B = PSC Input Module A PSCn Input A Waveform Generator A PSCOUTn0 OCRnRA = OCRnSA Part A PICRn PCNFEn PCNFn PCTLn Note: PASDLYn PFRCnB PFRCnA PSOCn n = 0, 1. The principle of the PSC is based on the use of a counter (PSC counter).
AT90PWM81/161 12.3.1 PSC2 Distinctive Feature Figure 12-2. PSC2 versus PSC1&PSC0 block diagram. PSC Counter PSCOUTn3 = POS23 Waveform Generator B PSCOUTn1 OCRnRB DATABUS = PSC Input Module B OCRnSB Part A = PSCn Input B Output Matrix PSC Input Module A PSCn Input A OCRnRA = PSCOUTn2 POS22 Waveform Generator A PSCOUTn0 OCRnSA Part B PICRn PCNFEn PCNFn PCTLn Note: PASDLYn PFRCnB PFRCnA POM2(PSC2 only) PSOCn n = 2. PSC2 has two supplementary outputs PSCOUT22 and PSCOUT23.
AT90PWM81/161 12.4 Signal Description Figure 12-3. PSC external block view. CLKPLL CLK I/O SYnIn StopOut OCRnRB[11:0] OCRnSB[11:0] OCRnRA[11:0] OCRnSA[11:0] OCRnRB[15:12] 12 PSCOUTn0 12 PSCOUTn1 12 (1) PSCOUTn2 12 (1) PSCOUTn3 4 (Flank Width Modulation) PICRn[11:0] 12 2 2 IRQ PSCn PSCINn Analog Comparator n Output StopIn SYnOut PSCnASY Note: 1. available only for PSC2. 2. n = 0, 1 or 2. 12.4.1 Input Description Table 12-1. Internal inputs.
AT90PWM81/161 Table 12-2. Name 12.4.2 Block inputs. Description Type width PSCINn Input 0 used for Retrigger or Fault functions Signal from 1st A C Input 1 used for Retrigger or Fault functions Signal PSCINnA Input 2 used for Retrigger or Fault functions Signal from 2nd A C Input 3 used for Retrigger or Fault functions Signal Output Description Table 12-3. Name Block outputs.
AT90PWM81/161 Figure 12-4. Cycle presentation in 1, 2, and 4 ramp mode. PSC Cycle Sub-Cycle A Sub-Cycle B 4 Ramp Mode Ramp A0 Ramp A1 Ramp B0 Ramp B1 2 Ramp Mode Ramp A Ramp B 1 Ramp Mode UPDATE Figure 12-5. Cycle presentation in centered mode. PSC Cycle Centered Mode UPDATE Ramps illustrate the output of the PSC counter included in the waveform generators. Centered Mode is like a one ramp mode which count down up and down.
AT90PWM81/161 Figure 12-6. PSCn0 & PSCn1 basic waveforms in Four Ramp mode. PSC Counter OCRnSA OCRnRA OCRnRB OCRnSB 0 0 On-Time 0 On-Time 1 PSCOUTn0 PSCOUTn1 Dead-Time 1 Dead-Time 0 PSC Cycle The input clock of PSC is given by CLKPSC.
AT90PWM81/161 Figure 12-7. PSCn0 & PSCn1 basic waveforms in Two Ramp mode. OCRnRA OCRnRB PSC Counter OCRnSA OCRnSB 0 0 On-Time 0 On-Time 1 PSCOUTn0 PSCOUTn1 Dead-Time 1 Dead-Time 0 PSC Cycle PSCOUTn0 and PSCOUTn1 signals are defined by On-Time 0, Dead-Time 0, On-Time 1 and Dead-Time 1 values with: On-Time 0 = (OCRnRAH/L - OCRnSAH/L) × 1/Fclkpsc On-Time 1 = (OCRnRBH/L - OCRnSBH/L) × 1/Fclkpsc Dead-Time 0 = (OCRnSAH/L + 1) × 1/Fclkpsc Dead-Time 1 = (OCRnSBH/L + 1) × 1/Fclkpsc Note: 12.5.2.
AT90PWM81/161 Figure 12-8. PSCn0 & PSCn1 basic waveforms in One Ramp mode. OCRnRB OCRnSB OCRnRA PSC Counter OCRnSA 0 On-Time 0 On-Time 1 PSCOUTn0 PSCOUTn1 Dead-Time 1 Dead-Time 0 PSC Cycle On-Time 0 = (OCRnRAH/L - OCRnSAH/L) × 1/Fclkpsc On-Time 1 = (OCRnRBH/L - OCRnSBH/L) × 1/Fclkpsc Dead-Time 0 = (OCRnSAH/L + 1) × 1/Fclkpsc Dead-Time 1 = (OCRnSBH/L - OCRnRAH/L) × 1/Fclkpsc Note: 12.5.2.4 Minimal value for Dead-Time 0 = 1/Fclkpsc.
AT90PWM81/161 Figure 12-9. PSCn0 & PSCn1 basic waveforms in Center Aligned mode. OCRnRB PSC Counter OCRnSB OCRnSA 0 On-Time 0 On-Time 1 On-Time 1 PSCOUTn0 PSCOUTn1 Dead-Time Dead-Time PSC Cycle On-Time 0 = 2 × OCRnSAH/L × 1/Fclkpsc On-Time 1 = 2 × (OCRnRBH/L - OCRnSBH/L + 1) × 1/Fclkpsc Dead-Time = (OCRnSBH/L - OCRnSAH/L) × 1/Fclkpsc PSC Cycle = 2 × (OCRnRBH/L + 1) × 1/Fclkpsc Note: Minimal value for PSC Cycle = 2 × 1/Fclkpsc. OCRnRAH/L is not used to control PSC Output waveform timing.
AT90PWM81/161 12.5.3 12.6 Fifty Percent Waveform Configuration When PSCOUTn0 and PSCOUTn1 have the same characteristics, it’s possible to configure the PSC in a Fifty Percent mode. When the PSC is in this configuration, it duplicates the OCRnSBH/L and OCRnRBH/L registers in OCRnSAH/L and OCRnRAH/L registers. So it is not necessary to program OCRnSAH/L and OCRnRAH/L registers.
AT90PWM81/161 12.7 Enhanced Resolution Lamp Ballast applications need an enhanced resolution down to 50Hz. The method to improve the normal resolution is based on Flank Width Modulation (also called Fractional Divider). Cycles are grouped into frames of 16 cycles. Cycles are modulated by a sequence given by the fractional divider number. The resulting output frequency is the average of the frequencies in the frame. The fractional divider (d) is given by OCRnRB[15:12].
AT90PWM81/161 Then the frequency resolution is divided by 16. In the example above, the resolution equals 25Hz.
AT90PWM81/161 Table 12-6. Distribution of fb2 in the modulated frame.
AT90PWM81/161 The waveform frequency is defined by the following equation: f CLK_PSCn 1 f PSCn = ------------------------------ = -------------------------------------------------------------------PSCnCycle ( OT0 + OT1 + DT0 + DT1 ) 12.7.2.2 Enhanced Mode The Enhanced Mode uses the previously described method to generate a high resolution frequency. Figure 12-13 gives an example of FWM with PBFMn1:0 = 00. Figure 12-13. Enhanced mode, timing diagram.
AT90PWM81/161 According to PSC n Input A Control Register (see “PFRCnA - PSC n Input A Control Register” on page 141), PSC n input A can act as a Retrigger or Fault input. Each part A or B can be triggered by up to four signals as defined per Table 12-18 on page 139 and Table 12-19 on page 139. Part A of PSC has also a blanking module allowing to cancel unwanted transitions which may appear on the PSC n input A during a certain period of time.
AT90PWM81/161 Figure 12-15. PSC input module B. PAOCnB PSCINn 0 0 0 AC2O: Analog Comparator Output 0 1 PSCINnA 1 0 AC3O:Analog Comparator Output PSC n Input B Digital Filter CLK PSC 1 1 PFLTEnB 1 PISELnB1 PISELnB0 PCAEnB PELEVnB PRFMnB3:0 4 Input Processing (retriggering ...) CLK PSC PSC Core (Counter, Waveform Generator, ...) Output Control CLK PSC 12.8.
AT90PWM81/161 Figure 12-16. PSCOUTn0 retrograde by PSCn Input A (edge retriggering). On-Time 0 On-Time 1 PSCOUTn0 PSCOUTn1 PSCn Input A (falling edge) PSCn Input A (rising edge) Dead-Time 0 Note: Dead-Time 1 This example is given in “Input Mode 8” in “2 or 4 ramp mode”. See Figure 12-33 on page 126 for details. Figure 12-17. PSCOUTn0 retriggered by PSCn Input A (level acting). On-Time 0 On-Time 1 PSCOUTn0 PSCOUTn1 PSCn Input A (high level) PSCn Input A (low level) Dead-Time 0 Note: 12.8.
AT90PWM81/161 Figure 12-18. PSCOUTn1 retriggered by PSCn Input B (edge retriggering). On-Time 0 On-Time 1 PSCOUTn0 PSCOUTn1 PSCn Input B (falling edge) PSCn Input B (rising edge) Dead-Time 0 Note: Dead-Time 1 Dead-Time 0 This example is given in “Input Mode 8” in “2 or 4 ramp mode”. See Figure 12-33 on page 126 for details. Figure 12-19. PSCOUTn1 retriggered by PSCn Input B (level acting).
AT90PWM81/161 Figure 12-20. Burst generation. OFF BURST PSCOUTn0 PSCOUTn1 PSCn Input A (high level) PSCn Input A (low level) 12.8.4 12.8.4.1 PSC Input Configuration The PSC Input Configuration is done by programming bits in configuration registers. Filter Enable If the “Filter Enable” bit is set, a digital filter of four cycles is inserted before evaluation of the signal.
AT90PWM81/161 - In 2- or 4-ramp mode, PSCn Input A is taken into account only during Dead-Time0 and OnTime0 period (respectively Dead-Time1 and On-Time1 for PSCn Input B). - In 1-ramp-mode PSC Input A or PSC Input B act on the whole ramp. 12.8.4.3 Input Mode Operation Thanks to 4 configuration bits (PRFM3:0), it’s possible to define the mode of the PSC input. Thanks to four configuration bits (PRFM3:0), it is possible to define all the modes of the PSCR input. These modes are listed in Table 12-7.
AT90PWM81/161 12.9 PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait Figure 12-22. PSCn behavior versus PSCn Input A in Fault Mode 1. DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSC Input A PSC Input B PSC Input A is taken into account during DT0 and OT0 only. It has no effect during DT1 and OT1. When PSC Input A event occurs, PSC releases PSCOUTn0, waits for PSC Input A inactive state and then jumps and executes DT1 plus OT1. Figure 12-23.
AT90PWM81/161 12.10 PSC Input Mode 2: Stop signal, Execute Opposite Pulse and Wait Figure 12-24. PSCn behavior versus PSCn Input A in Fault Mode 2. DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSC Input A PSC Input B PSC Input A is take into account during DT0 and OT0 only. It has no effect during DT1 and OT1. When PSCn Input A event occurs, PSC releases PSCOUTn0, jumps and executes DT1 plus OT1 and then waits for PSC Input A inactive state.
AT90PWM81/161 12.11 PSC Input Mode 3: Stop signal, Execute Opposite Pulse while Fault active Figure 12-26. PSCn behavior versus PSCn Input A in Mode 3. DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT1 OT1 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSC Input A PSC Input B PSC Input A is taken into account during DT0 and OT0 only. It has no effect during DT1 and OT1. When PSC Input A event occurs, PSC releases PSCOUTn0, jumps and executes DT1 plus OT1 plus DT0 while PSC Input A is in active state.
AT90PWM81/161 12.12 PSC Input Mode 4: Deactivate outputs without changing timing Figure 12-28. PSC behavior versus PSCn Input A or Input B in Mode 4. DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSCn Input A or PSCn Input B Figure 12-29. PSC behavior versus PSCn Input A or Input B in Fault Mode 4.
AT90PWM81/161 12.14 PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait Figure 12-31. PSC behavior versus PSCn Input A in Fault Mode 6. DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSCn Input A or PSCn Input B Used in Fault mode 6, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1. 12.15 PSC Input Mode 7: Halt PSC and Wait for Software Action Figure 12-32. PSC behavior versus PSCn Input A in Fault Mode 7.
AT90PWM81/161 12.16 PSC Input Mode 8: Edge Retrigger PSC Figure 12-33. PSC behavior versus PSCn Input A in Mode 8. DT0 OT0 DT1 DT0 OT0 OT1 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSCn Input A The output frequency is modulated by the occurrence of significative edge of retriggering input. Figure 12-34. PSC behavior versus PSCn Input B in Mode 8.
AT90PWM81/161 12.17 PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC Figure 12-35. PSC behavior versus PSCn Input A in Mode 9. DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSCn Input A The output frequency is not modified by the occurrence of significative edge of retriggering input. Only the output is deactivated when significative edge on retriggering input occurs.
AT90PWM81/161 12.18 PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Deactivate Output Figure 12-37. PSC behavior versus PSCn Input A in Mode 14. DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSCn Input A The output frequency is not modified by the occurrence of significative edge of retriggering input. Figure 12-38. PSC behavior versus PSCn Input B in Mode 14.
AT90PWM81/161 Table 12-8. Available input modes according to running modes. (Continued) Input mode number: 1 ramp mode 2 ramp mode 4 ramp mode Centered mode 7 Valid Valid Valid Valid 8 Valid Valid Valid Do not use 9 Valid Valid Valid Do not use Valid Valid Do not use 10 11 Do not use 12 13 12.18.2 14 Valid 15 Do not use Event Capture The PSC can capture the value of time (PSC counter) when a retrigger event or fault event occurs on PSC inputs.
AT90PWM81/161 12.19.2 PSCOUT22 & PSCOUT23 Selectors PSC 2 has two supplementary outputs PSCOUT22 and PSCOUT23. According to POS22 and POS23 bits in PSOC2 register, PSCOUT22 and PSCOUT23 duplicate PSCOUT20 and PSCOU21. If POS22 bit in PSOC2 register is clear, PSCOUT22 duplicates PSCOUT20. If POS22 bit in PSOC2 register is set, PSCOUT22 duplicates PSCOUT21. If POS23 bit in PSOC2 register is clear, PSCOUT23 duplicates PSCOUT21. If POS23 bit in PSOC2 register is set, PSCOUT23 duplicates PSCOUT20. Figure 12-39.
AT90PWM81/161 12.20 Analog Synchronization PSC generates a signal to synchronize the sample and hold or the ADC start; synchronization is mandatory for measurements. This signal can be selected between all falling or rising edge of PSCn0 or PSCn1 outputs as defined per Table 12-11 on page 134 and Table 12-12 on page 135. The signal can be shifted by a digital delay defined by the register PASDLY.
AT90PWM81/161 12.22 PSC Synchronization Note: In AT90PWM81/161, this feature is not relevant and PRUN2, PARUN2 are stuck at zero. 2 or 3 PSC can be synchronized together. In this case, two waveform alignments are possible: • The waveforms are center aligned in the Center Aligned mode if master and slaves are all with the same PSC period (which is the natural use). • The waveforms are edge aligned in the 1, 2 or 4 ramp mode Figure 12-41. PSC run synchronization.
AT90PWM81/161 A PSC which receive its Run signal from the previous PSC transmits its fault signal (if enabled) to this previous PSC. So a slave PSC propagates its fault events when they are configured and enabled. 12.23 PSC Clock Sources PSC must be able to generate high frequency with enhanced resolution. Each PSC has two clock inputs: • CLK PLL from the PLL • CLK I/O Figure 12-42. Clock selection.
AT90PWM81/161 12.24 Interrupts This section describes the specifics of the interrupt handling as performed in AT90PWM81/161. 12.24.
AT90PWM81/161 Table 12-12. Synchronization source description in centered mode.
AT90PWM81/161 12.25.4 OCRnSBH and OCRnSBL - Output Compare SB Register Bit 7 6 5 4 3 – – – – OCRnSB[11:8] 2 1 0 OCRnSBH OCRnSB[7:0] 12.25.5 OCRnSBL Read/Write W W W W W W W W Initial Value 0 0 0 0 0 0 0 0 3 2 1 0 OCRnRBH and OCRnRBL - Output Compare RB Register Bit 7 6 5 4 OCRnRB[15:12] OCRnRB[11:8] OCRnRBH OCRnRB[7:0] OCRnRBL Read/Write W W W W W W W W Initial Value 0 0 0 0 0 0 0 0 Note: n = 0 to 2 according to PSC number.
AT90PWM81/161 • Bit 5 – PLOCKn: PSC n Lock When this bit is set, the Output Compare Registers RA, RB, SA, SB, the Output Matrix POM2 and the PSC Output Configuration PSOCn can be written without disturbing the PSC cycles. The update of the PSC internal registers will be done if the LOCK bit is released to zero. • Bit 4:3 – PMODEn1: 0: PSC n Mode Select the mode of PSC. Table 12-13. PSC n mode selection.
AT90PWM81/161 Table 12-14. Analog signal synchronization or Input Blanking mode selection.
AT90PWM81/161 • Bit 2– PELEVnB1: PSC n Input Select for part B Together with PELEVnB0, defines active edge or level on PSC part B. Table 12-17. PSC edge & level input selection.
AT90PWM81/161 See also the bit definition Section “Bit 7, 6, 5– PASDLKn(2:0): Analog Synchronization Output Delay or Input Blanking select”, page 137 and Section “Bit 5:4 – PSYNCn1:0: Synchronization Out for ADC Selection”, page 134. 12.25.
AT90PWM81/161 12.25.10 PFRCnA - PSC n Input A Control Register Bit 7 6 PCAEnA PISELnA0 PELEVnA0 PFLTEnA 5 4 3 2 1 0 PRFMnA3 PRFMnA2 PRFMnA1 PRFMnA0 PFRCnA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 5 4 3 2 1 0 12.25.
AT90PWM81/161 Table 12-21. Level sensitivity and Fault Mode operation.
AT90PWM81/161 • Bit 7 – POMV2B3: Output Matrix Output B Ramp 3 This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 3. • Bit 6 – POMV2B2: Output Matrix Output B Ramp 2 This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 2. • Bit 5 – POMV2B1: Output Matrix Output B Ramp 1 This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 1. • Bit 4 – POMV2B0: Output Matrix Output B Ramp 0 This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 0.
AT90PWM81/161 12.26.3 PIFR2 - PSC2 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 POAC2B POAC2A PSEI2 PEV2B PEV2A PRN21 PRN20 PEOP2 Read/Write R R R/W R/W R/W R R R/W Initial Value 0 0 0 0 0 0 0 0 PIFR2 • Bit 7 – POACnB: PSC n Output B Activity This bit is set by hardware each time the output PSCOUTn1 changes from 0 to 1 or from 1 to 0. Must be cleared by software by writing a one to its location.
AT90PWM81/161 Table 12-22. PSC n ramp number description. PRNn1 PRNn0 Description 0 0 The last event which has generated an interrupt occurred during ramp 1 0 1 The last event which has generated an interrupt occurred during ramp 2 1 0 The last event which has generated an interrupt occurred during ramp 3 1 1 The last event which has generated an interrupt occurred during ramp 4 • Bit 0 – PEOPn: End Of PSC n Interrupt This bit is set by hardware when PSC n achieves its whole cycle.
AT90PWM81/161 If PSC2RB fuse equals 1 (unprogrammed), PSCOUT20 & PSCOUT21 keep a standard port behavior. If PSC2RB fuse equals 0 (programmed), PSCOUT20 & PSCOUT21 are forced at reset to low level or high level according to PSCRV fuse bit. In this second case, PSCOUT20 & PSCOUT21 keep the forced state until PSOC2 register is written. If PSC2RBA fuse equals 1 (unprogrammed), PSCOUT22 & PSCOUT23 keep a standard port behavior.
AT90PWM81/161 13. Reduced Power Stage Controller – (PSCR) The Reduced Power Stage Controller is a high performance waveform controller. 13.1 Features • • • • • • • • • PWM waveform generation function (two complementary programmable outputs) Dead time control Standard mode up to 12-bit resolution Enhanced resolution up to 16 bits Frequency up to 64Mhz Conditional waveform on external events (zero crossing, current sensing ...
AT90PWM81/161 13.3 PSCR Description Figure 13-1. Power Stage Controller block diagram. PSCR Counter = Waveform Gererator B PSCOUTr1 PSC Input Module B PSCr Input B OCRrRB DATABUS = OCRrSB Part B = PSC Input Module A PSCr Input A Waveform Gererator A PSCOUTr0 OCRrRA = OCRrSA Part A PICRr PCNFr PCTLr PFRCrB PFRCrA PSOCr The principle of the PSCR is based on the use of a counter (PSCR counter).
AT90PWM81/161 13.4 Signal Description Figure 13-2. PSCR external block view. CLK PLL CLK I/O OCRrRB[11:0] OCRrSB[11:0] OCRrRA[11:0] OCRrSA[11:0] 12 PSCOUTr0 12 PSCOUTr1 12 12 PICRr[11:0] 12 3 IRQ PSCr PSCINr Analog Comparator Output PSCrASY 13.4.1 Input Description Table 13-1. Name Internal inputs.
AT90PWM81/161 Table 13-2. Name 13.4.2 Block inputs. Description Type width PSCINr Input 0 used for retrigger or fault functions Signal From analog comparator Input 1 used for retrigger or fault functions Signal PSCINrA Input 2 used for retrigger or fault functions Signal PSCINrB Input 3 used for retrigger or fault functions Signal Output Description Table 13-3. Name Block outputs.
AT90PWM81/161 13.5 13.5.1 Functional Description Waveform Cycles The waveform generated by PSCR can be described as a sequence of two waveforms. The first waveform is relative to PSCOUTr0 output and part A of PSC. The part of this waveform is sub-cycle A in Figure 13-3. The second waveform is relative to PSCOUTr1 output and part B of PSC. The part of this waveform is sub-cycle B in Figure 13-3. The complete waveform is ended with the end of sub-cycle B. It means at the end of waveform B. Figure 13-3.
AT90PWM81/161 The waveform frequency is defined by the following equation: f CLK_PSCn 1 f PSCn = ------------------------------ = -------------------------------------------------------------------PSCnCycle ( OT0 + OT1 + DT0 + DT1 ) 13.5.2.1 Four Ramp Mode In Four Ramp mode, each time in a cycle has its own definition. Figure 13-4. PSCr0 & PSCr1 basic waveforms in Four Ramp mode.
AT90PWM81/161 13.5.2.2 Two Ramp Mode In Two Ramp mode, the whole cycle is divided in two moments: • One moment for PSCr0 description with OT0 which gives the time of the whole moment • One moment for PSCr1 description with OT1 which gives the time of the whole moment Figure 13-5. PSCr0 & PSCr1 basic waveforms in Two Ramp mode.
AT90PWM81/161 Figure 13-6. PSCr0 & PSCr1 basic waveforms in One Ramp mode. OCRnRB OCRnSB OCRnRA PSC Counter OCRnSA 0 On-Time 0 On-Time 1 PSCOUTn0 PSCOUTn1 Dead-Time 1 Dead-Time 0 PSC Cycle On-Time 0 = (OCRrRAH/L - OCRrSAH/L) × 1/Fclkpsc On-Time 1 = (OCRrRBH/L - OCRrSBH/L) × 1/Fclkpsc Dead-Time 0 = (OCRrSAH/L + 1) × 1/Fclkpsc Dead-Time 1 = (OCRrSBH/L - OCRrRAH/L) × 1/Fclkpsc Note: 13.5.3 13.6 Minimal value for Dead-Time 0 = 1/Fclkpsc.
AT90PWM81/161 Figure 13-7. Update at the end of complete PSCR cycle. Regulation Loop Calculation Writting in PSC Registers Software Cycle With Set i Cycle With Set i Cycle With Set i Request for an Update Cycle With Set i PSC Cycle With Set j End of Cycle The software can stop the cycle before the end to update the values and restart a new PSCR cycle. 13.6.1 Value Update Synchronization New timing values or PSCR output configuration can be written during the PSCR cycle.
AT90PWM81/161 Figure 13-8. PSCR input module. PAOCrA (PAOCrB) PSCINr 0 0 0 AC1O: Analog Comparator Output 0 1 PSCINrA 1 0 PSCR Input A (PSCR Input B) Digital Filter CLK PSC PSCINrB 1 1 PFLTErA (PFLTErB) 1 PELEVrA / PCAErA (PELEVrB) (PCAErB) PISELrA1 PISELrA0 (PISELrB1) (PISELrB0) PRFMrA3:0 (PRFMrB3:0) 2 4 Input Processing (retriggering ...) CLK PSC PSC Core (Counter, Waveform Generator, ...) Output Control PSCOUTr0 (PSCOUTr1) CLK PSC 13.8.
AT90PWM81/161 Figure 13-9. PSCOUTr0 retriggered by PSCr Input A (edge retriggering). On-Time 0 On-Time 1 PSCOUTn0 PSCOUTn1 PSCn Input A (falling edge) PSCn Input A (rising edge) Dead-Time 0 Note: Dead-Time 1 This example is given in “Input Mode 8” in “2 or 4 ramp mode”. See Figure 13-26 on page 166 for details. Figure 13-10. PSCOUTr0 retriggered by PSCr Input A (level acting). On-Time 0 On-Time 1 PSCOUTn0 PSCOUTn1 PSCn Input A (high level) PSCn Input A (low level) Dead-Time 0 Note: 13.8.
AT90PWM81/161 As the period of the cycle decreases, the instantaneous frequency of the two outputs increases. Figure 13-11. PSCOUTr1 retriggered by PSCr Input B (edge retriggering). On-Time 0 On-Time 1 PSCOUTn0 PSCOUTn1 PSCn Input B (falling edge) PSCn Input B (rising edge) Dead-Time 0 Note: Dead-Time 1 Dead-Time 0 This example is given in “Input Mode 8” in “2 or 4 ramp mode”. See Figure 13-26 on page 166 for details. Figure 13-12. PSCOUTr1 retriggered by PSCr Input B (level acting).
AT90PWM81/161 Figure 13-13. Burst generation. OFF BURST PSCOUTn0 PSCOUTn1 PSCn Input A (high level) PSCn Input A (low level) 13.8.4 13.8.4.1 PSCR Input Configuration The PSCR Input Configuration is done by programming bits in configuration registers. Filter Enable If the “Filter Enable” bit is set, a digital filter of four cycles is inserted before evaluation of the signal.
AT90PWM81/161 - In 2- or 4-ramp mode, PSCr Input A is taken into account only during Dead-Time0 and OnTime0 period (respectively Dead-Time1 and On-Time1 for PSCr Input B). - In 1-ramp-mode PSCR Input A or PSCR Input B act on the whole ramp. 13.8.4.3 Input Mode Operation Thanks to four configuration bits (PRFM3:0), it is possible to define all the modes of the PSCR input. These modes are listed in Table 13-5. Table 13-5. PSCR input mode operation.
AT90PWM81/161 13.9 PSCR Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait Figure 13-15. PSCr behavior versus PSCr Input A in Fault Mode 1. DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSC Input A PSC Input B PSCR Input A is taken into account during DT0 and OT0 only. It has no effect during DT1 and OT1. When PSCR Input A event occurs, PSCR releases PSCOUTr0, waits for PSCR Input A inactive state and then jumps and executes DT1 plus OT1. Figure 13-16.
AT90PWM81/161 13.10 PSCR Input Mode 2: Stop signal, Execute Opposite Dead-Time and Wait Figure 13-17. PSCr behavior versus PSCr Input A in Fault Mode 2. DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSC Input A PSC Input B PSCR Input A is take into account during DT0 and OT0 only. It has no effect during DT1 and OT1. When PSCr Input A event occurs, PSCR releases PSCOUTr0, jumps and executes DT1 plus OT1 and then waits for PSCR Input A inactive state.
AT90PWM81/161 13.11 PSCR Input Mode 3: Stop signal, Execute Opposite while Fault active Figure 13-19. PSCr behavior versus PSCr Input A in Mode 3. DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT1 OT1 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSC Input A PSC Input B PSCR Input A is taken into account during DT0 and OT0 only. It has no effect during DT1 and OT1. When PSCR Input A event occurs, PSCR releases PSCOUTr0, jumps and executes DT1 plus OT1 plus DT0 while PSCR Input A is in active state.
AT90PWM81/161 13.12 PSCR Input Mode 4: Deactivate outputs without changing timing Figure 13-21. PSCR behavior versus PSCr Input A or Input B in Mode 4. DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSCn Input A or PSCn Input B Figure 13-22. PSCR behavior versus PSCr Input A or Input B in Fault Mode 4.
AT90PWM81/161 13.14 PSCR Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait Figure 13-24. PSCR behavior versus PSCr Input A in Fault Mode 6. DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSCn Input A or PSCn Input B Used in Fault mode 6, PSCr Input A or PSCr Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1. 13.15 PSCR Input Mode 7: Halt PSCR and Wait for Software Action Figure 13-25. PSCR behavior versus PSCr Input A in Fault Mode 7.
AT90PWM81/161 13.16 PSCR Input Mode 8: Edge Retrigger PSC Figure 13-26. PSCR behavior versus PSCr Input A in Mode 8. DT0 OT0 DT1 DT0 OT0 OT1 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSCn Input A The output frequency is modulated by the occurrence of significative edge of retriggering input. Figure 13-27. PSCR behavior versus PSCr Input B in Mode 8.
AT90PWM81/161 13.17 PSCR Input Mode 9: Fixed Frequency Edge Retrigger PSC Figure 13-28. PSCR behavior versus PSCr Input A in Mode 9. DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSCn Input A The output frequency is not modified by the occurrence of significative edge of retriggering input. Only the output is deactivated when significative edge on retriggering input occurs.
AT90PWM81/161 13.18 PSCR Input Mode 14: Fixed Frequency Edge Retrigger PSCR and Deactivate Output Figure 13-30. PSCR behavior versus PSCr Input A in Mode 14. DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSCn Input A The output frequency is not modified by the occurrence of significative edge of retriggering input. Figure 13-31. PSCR behavior versus PSCr Input B in Mode 14.
AT90PWM81/161 Table 13-6. Available input modes according to running modes. (Continued) Input mode number: 1 Ramp mode 2 Ramp mode 4 Ramp mode Valid Valid 10 11 Do not use 12 13 13.18.2 14 Valid 15 Do not use Event Capture The PSCR can capture the value of time (PSCR counter) when a retrigger event or fault event occurs on PSCR inputs. This value can be read by software in PICRrH/L register. 13.18.
AT90PWM81/161 Figure 13-32. Clock selection. CLK 1 PLL CK CK CK/4 CK/32 CK/256 01 10 11 0 I/O 00 CLK PRESCALER PCLKSELr PPREr1/0 CLK PSCr PCLKSELr bit in PSCR Configuration register (PCNFr) is used to select the clock source. PPREr1/0 bits in PSCR Control Register (PCTLr) are used to select the divide factor of the clock. Table 13-7. Output clock versus selection and prescaler.
AT90PWM81/161 13.23 PSCR Register Definition 13.23.1 PSOC0 - PSCR Synchro and Output Configuration Bit 7 6 4 3 2 1 PISEL0A1 PISEL0B1 PSYNC01 5 PSYNC00 - POEN0B - 0 POEN0A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PSOC0 • Bit 7– PISEL0A1: PSC Input Select for part A Together with PISEL0A0, defines active signal on PSCR part A. Table 13-8. PSC trigger & fault input selection.
AT90PWM81/161 When this bit is set, I/O pin affected to PSCOUT01 is connected to the PSCR waveform generator B output and is set and clear according to the PSCR operation. • Bit 1 – Reserved • Bit 0 – POEN0A: PSCR OUT Part A Output Enable When this bit is clear, I/O pin affected to PSCOUT00 acts as a standard port. When this bit is set, I/O pin affected to PSCOUT00 is connected to the PSCR waveform generator A output and is set and clear according to the PSCR operation. 13.23.
AT90PWM81/161 13.23.6 PCNF0 - PSCR Configuration Register Bit 7 6 PFIFTY0 PALOCK0 PLOCK0 5 4 PMODE01 PMODE00 POP0 3 2 PCLKSEL0 - 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCNF0 • Bit 7 - PFIFTY0: PSCR Fifty Writing this bit to one, set the PSCR in a fifty percent mode where only OCR0RBH/L and OCR0SBH/L are used. They are duplicated in OCR0RAH/L and OCR0SAH/L during the update of OCR0RBH/L.
AT90PWM81/161 13.23.7 PCTL0 - PSCR Control Register Bit 7 6 5 4 3 2 1 0 PPRE01 PPRE00 PBFM01 PAOC0B PAOC0A PBFM00 PCCYC0 PRUN0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCTL0 • Bit 7:6 – PPRE01:0 : PSCR Prescaler Select This two bits select the PSCR input clock division factor. All generated waveform will be modified by this factor. Table 13-12. PSCR prescaler selection.
AT90PWM81/161 • Bit 5- PBFM01: Balance Flank Width Modulation, bit 1 Defines the Flank Width Modulation, together with PBFM00 bit. Table 13-13. Flank Width mode selection. PBFM01 PBFM00 Description 0 0 Flank Width Modulation operates on RB (On-Time 1 only) 0 1 Flank Width Modulation operates on RB + RA (On-Time 0 and OnTime 1) 1 0 Flank Width Modulation operates on SB (Dead-Time 1 only) (1) 1 1 Flank Width Modulation operates on SB +SA (Dead-Time 0 and Dead-Time 1) Note: 1.
AT90PWM81/161 • Bit 7 – PCAE0x: PSCR Capture Enable Input Part x Writing this bit to one enables the capture function when external event occurs on input selected as input for Part x (see PISEL0x0 bit in the same register). • Bit 6 – PISEL0x0: PSCR Input Select for Part x Together with PISEL0x1 in PSOC0 register, defines active signal on PSC module A. See Table 13-8 on page 171 and Table 13-9 on page 171.
AT90PWM81/161 Table 13-14. Level sensitivity and Fault mode operation. (Continued) PRFM0x3:0 Description 1010b Reserved (do not use) 1011b 1100b 1101b “PSCR Input Mode 14: Fixed Frequency Edge Retrigger PSCR and Deactivate Output”, page 168 Reserved (do not use) 1110b 1111b 13.23.
AT90PWM81/161 • Bit 1– PEOEPE0: PSCR End Of Enhanced Cycle Interrupt Enable When this bit is set, an interrupt is generated when PSC reduced reaches the end of the 15th PSC cycle. This allows to update the PSCR values in the interrupt routine and to start a new enhanced cycle with the new values at the next PSCR cycle end. • Bit 0 – PEOPE0: PSCR End Of Cycle Interrupt Enable When this bit is set, an interrupt is generated when PSCR reaches the end of the whole cycle. 13.23.
AT90PWM81/161 Table 13-15. PSCR ramp number description. PRN01 PRN00 Description 0 0 The last event which has generated an interrupt occurred during ramp 1 0 1 The last event which has generated an interrupt occurred during ramp 2 1 0 The last event which has generated an interrupt occurred during ramp 3 1 1 The last event which has generated an interrupt occurred during ramp 4 • Bit 0 – PEOP0: End Of PSCR Interrupt This bit is set by hardware when PSCR achieves its whole cycle.
AT90PWM81/161 14. Serial Peripheral Interface – SPI: 14.1 Features • • • • • • • • 14.
AT90PWM81/161 The interconnection between Master and Slave CPUs with SPI is shown in Figure 14-2. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data.
AT90PWM81/161 When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 14-1. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 73. Table 14-1. Pin SPI pin overrides (1). Direction, Master SPI Direction, Slave SPI MOSI User defined Input MISO Input User defined SCK User defined Input SS User defined Input Note: 1.
AT90PWM81/161 Assembly code example (1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<
AT90PWM81/161 Assembly code example (1) SPI_SlaveInit: ; Set MISO output, all others input ldi r17,(1<
AT90PWM81/161 means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high. The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master clock generator. When the SS pin is driven high, the SPI slave will immediately reset the send and receive logic, and drop any partially received data in the Shift Register. 14.3.
AT90PWM81/161 Figure 14-3. SPI transfer format with CPHA = 0. SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Figure 14-4. SPI transfer format with CPHA = 1. SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) LSB first (DORD = 1) 14.5 14.5.
AT90PWM81/161 • Bit 5 – DORD: Data Order When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first. • Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set.
AT90PWM81/161 14.5.2 SPSR - SPI Status Register Bit 7 6 5 4 3 2 1 0 SPIF WCOL – – – – – SPI2X Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 SPSR • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF flag.
AT90PWM81/161 15. Voltage Reference and Temperature Sensor 15.1 Features • Accurate voltage reference of 2.56V • Internal temperature sensor • Possibility for runtime compensation of temperature drift in both voltage reference and on-chip oscillators • Low power consumption 15.2 On Chip voltage Reference and Temperature sensor overview A low power band-gap reference provides AT90PWM81/161 with an accurate On-chip Bandgap voltage of 1.100V (Vbg).
AT90PWM81/161 Figure 15-1. Reference circuitry. Aref SW0 REFS0, REFS1 are used to control SW0..3 AVcc SW1 VPTAT Vref Voltage Reference SW2 Vbg /1.60 /2.13 BG Reference BG Calibration Fuses /3.20 ADC BG Calibration Registers BGCCR, BGCRR /6.40 Comp SW3 AT90PWM81/161 has an On-chip temperature sensor for monitoring the die temperature. A voltage Proportional-To-Absolute-Temperature, VPTAT, is generated in the voltage reference circuit and after buffering, is connected to the ADC multiplexer.
AT90PWM81/161 • Bit 7:4 – Res: Reserved Bit This bit is reserved for future use. • Bit 3:0 – BGCC3:0: BG Calibration of PTAT Current These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary coded, so the lowest value for Vbg is reached when BGCC3:0 is 0000 and the maximum value when BGCC3:0 is 1111. The step size is approximately 5mV. Updating the BGCC bits will affect the BOD detection level. The BOD will react quickly to the new detection level. 15.3.
AT90PWM81/161 Figure 15-2. Illustration of Vbg as a function of temperature. 1.5 BGCRR is used to move the top of the Vbg curve to the center of the temperature range of interest 1.0 Temperature range of interest 0.5 -40 -20 -0 20 40 60 80 100 Temperature (°C) 15.4 Temperature Measurement The temperature measurement is based on an on-chip temperature sensor that is coupled to a single ended ADC12 channel, as shown on Figure 15-3. Figure 15-3. Temperature sensor circuitry.
AT90PWM81/161 correlation to temperature and the typical accuracy of the temperature measurement is ±10°C after offset calibration. Table 15-1. Temperature vs. sensor output voltage (typical case). Temperature -40°C 25°C 105°C 125°C Voltage (mV) 600 762 1012 ADC 240 305 405 The values described in Table 15-1 are typical values. However, due to the process variation the temperature sensor output voltage varies from one chip to another.
AT90PWM81/161 16. Analog Comparator The Analog Comparator compares the input values on the positive pin ACMPx and negative pin ACMPM or ACMPMx. 16.1 Features • • • • • 16.2 Three analog comparators High speed analog comparators ±25mV or ±10mV or 0 hysteresis Four reference levels Generation of configurable interrupts Overview The AT90PWM81/161 features three fast analog comparators.
AT90PWM81/161 Figure 16-1. Analog comparator block diagram.
AT90PWM81/161 Figure 16-2. Comparator PSC links. ACMP1 + ACMPM1 - AC1EN PSCINr PSCINrA PSCINrB PSCR PSCIN2 ACMP2 + ACMPM2 AC2EN PSCIN2A PSC2 ACMP3 + ACMPM3 - AC3EN 16.3 Shared pins between Analog Comparator and ADC Several Analog comparators input pins can also be used as ADC inputs, so it is possible to measure the comparison voltages. However, when a comparator input is selected as the ADC input, a spike occurs during the sampling phase of the ADC.
AT90PWM81/161 16.4.1 AC1CON - Analog Comparator 1 Control Register Bit 7 6 5 4 3 2 1 0 AC1EN AC1IE AC1IS1 AC1IS0 - AC1M2 AC1M1 AC1M0 Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 AC1CON • Bit 7– AC1EN: Analog Comparator 1 Enable Bit Set this bit to enable the analog comparator 1. Clear this bit to disable the analog comparator 1. • Bit 6– AC1IE: Analog Comparator 1 Interrupt Enable bit Set this bit to enable the analog comparator 1 interrupt.
AT90PWM81/161 16.4.2 AC2CON - Analog Comparator 2 Control Register Bit 7 6 5 4 3 2 1 0 AC2EN AC2IE AC2IS1 AC2IS0 - AC2M2 AC2M1 AC2M0 Read/Write R/W R/W R/W R/W -R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 AC2CON • Bit 7– AC2EN: Analog Comparator 2 Enable bit Set this bit to enable the analog comparator 2. Clear this bit to disable the analog comparator 2. • Bit 6– AC2IE: Analog Comparator 2 Interrupt Enable bit Set this bit to enable the analog comparator 2 interrupt.
AT90PWM81/161 16.4.3 AC3CON - Analog Comparator 3 Control Register Bit 7 6 5 4 3 2 1 0 AC3EN AC3IE AC3IS1 AC3IS0 AC3OEA AC3M2 AC3M1 AC3M0 Read/Write R/W R/W R/W R/W - R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 AC3CON • Bit 7– AC3EN: Analog Comparator 3 Enable Bit Set this bit to enable the analog comparator 3. Clear this bit to disable the analog comparator 3.
AT90PWM81/161 16.4.4 ACnECON - Analog Comparator n Extended Control Register Bit 7 6 Read/Write Initial Value 0 0 5 4 3 2 1 0 ACnOI ACnOE AC1ICE ACnH2 ACnH1 ACnH0 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 ACnECON • Bit 7..6– Reserved • Bit 5– AC1OI: Analog Comparator n Output Invert Set this bit to invert the analog comparator n output. Clear this bit to keep the analog comparator n output.
AT90PWM81/161 16.4.5 ACSR - Analog Comparator Status Register Bit 7 6 5 4 3 2 1 0 AC3IF AC2IF AC1IF - AC3O AC2O AC1O - Read/Write R/W R/W R/W R/W - R R R Initial Value 0 0 0 0 0 0 0 0 ACSR • Bit 7– AC3IF: Analog Comparator 3 Interrupt Flag Bit This bit is set by hardware when comparator 3 output event triggers off the interrupt mode defined by AC3IS1 and AC3IS0 bits in AC3CON register.
AT90PWM81/161 16.4.6 DIDR0 - Digital Input Disable Register 0 Bit 7 6 5 4 ADC8D ACMP3D ADC7D AMP0-D ADC5D ACMP2D ADC4D ADC3D ACMP3MD ACMPMD 3 2 1 0 ADC2D ADC1D ACMP2MD ADC0D ACMP1D Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DIDR0 • Bit 7:0 – ACMPMxD and ACMPxD: ACMPxMD, ACMPxD & APM0+Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding Analog pin is disabled.
AT90PWM81/161 17. Analog to Digital Converter - ADC 17.1 Features • • • • • • • • • • • • • • • 10-bit resolution 0.5LSB integral non-linearity ±2LSB absolute accuracy 8µs - 250µs conversion time Up to 120kSPS at maximum resolution 11 multiplexed single ended input channels One differential input channels with accurate (5%) programmable gain 5, 10, 20, and 40 Optional left adjustment for ADC result readout 0 - VCC ADC input voltage range Selectable 2.
AT90PWM81/161 Figure 17-1. Analog to digital converter block schematic. AREF/ADC6 AVCC Internal 2.
AT90PWM81/161 17.2 Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1LSB. Optionally, AVCC or an internal 2.56V reference voltage may be connected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity.
AT90PWM81/161 vated by setting the bit ADSSEN in ADCSRB register. In this case the synchronization signal is blocked until the ADCH registed is read. Figure 17-2. ADC auto trigger logic. ADTS[2:0] PRESCALER START CLKADC ADATE ADIF SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished.
AT90PWM81/161 The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. See “Changing Channel or Reference Selection” on page 209 for details on differential conversion timing.
AT90PWM81/161 Figure 17-5. ADC timing diagram, single conversion. One Conversion 2 1 Cycle Number 3 5 4 6 7 8 9 10 11 12 Next Conversion 13 14 15 16 1 2 3 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete MUX and REFS Update MUX and REFS Update Figure 17-6. ADC timing diagram, auto triggered conversion.
AT90PWM81/161 Table 17-1. ADC conversion time. Condition Sample & hold (cycles from start of conversion) First conversion Normal conversion, single ended Auto triggered conversion 13.5 3.5 4 25 15.5 16 Conversion time (cycles) 17.5 Changing Channel or Reference Selection The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access.
AT90PWM81/161 • In Free Running mode, because the amplifier clear the ADSC bit at the end of an amplified conversion, it is not possible to use the free running mode, unless ADSC bit is set again by soft at the end of each conversion 17.5.2 ADC Voltage Reference The reference voltage for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as either AVCC, internal 2.56V reference, or external AREF pin.
AT90PWM81/161 request will be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power consumption.
AT90PWM81/161 a. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. b. The AVCC pin on the device should be connected to the digital VCC supply voltage via an LC network as shown in Figure 17-9. c. Use the ADC noise canceler function to reduce induced noise from the CPU. d.
AT90PWM81/161 Figure 17-10. Offset error. Output Code Ideal ADC Actual ADC Offset Error VREF Input Voltage • Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5LSB below maximum). Ideal value: 0LSB Figure 17-11. Gain error.
AT90PWM81/161 Figure 17-12. Integral non-linearity (INL). Output Code INL Ideal ADC Actual ADC VREF Input Voltage • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1LSB). Ideal value: 0LSB Figure 17-13. Differential non-linearity (DNL).
AT90PWM81/161 17.7 ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). For single ended conversion, the result is: V IN ⋅ 1023 ADC = -----------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 17-3 on page 218 and Table 17-4 on page 218). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage.
AT90PWM81/161 Figure 17-14. Differential measurement range.
AT90PWM81/161 Table 17-2. Correlation between input voltage and output codes. VADCn Read code Corresponding decimal value VADCm + VREF /GAIN 0x1FF 511 VADCm + 0.999 VREF /GAIN 0x1FF 511 VADCm + 0.998 VREF /GAIN 0x1FE 510 ... ... ... VADCm + 0.001 VREF /GAIN 0x001 1 VADCm 0x000 0 VADCm - 0.001 VREF /GAIN 0x3FF -1 ... ... ... VADCm - 0.999 VREF /GAIN 0x201 -511 VADCm - VREF /GAIN 0x200 -512 Example 1: – ADMUX = 0xED (ADC3 - ADC2, 10× gain, 2.
AT90PWM81/161 • Bit 7, 6 – REFS1, 0: ADC VREF Selection Bits These 2 bits determine the voltage reference for the ADC and for the other analog devices. The different setting are shown in Table 17-3. Table 17-3. REFS1 ADC voltage reference selection. REFS0 Description Voltage reference PE3/AREF pin External voltage reference 0 0 External VREF 0 1 AVCC 1 0 Internal 2.56V reference voltage External capacitor for decoupling of the internal reference voltage 1 1 Internal 2.
AT90PWM81/161 Table 17-4. ADC input channel selection. (Continued) MUX3 MUX2 MUX1 MUX0 Description 1 1 0 0 Temp sensor (Vtemp) 1 1 0 1 VCC/4 1 1 1 0 Bandgap (Vbg) 1 1 1 1 GND If these bits are changed during a conversion, the change will not take effect until this conversion is complete (it means while the ADIF bit in ADCSRA register is set). 17.8.
AT90PWM81/161 Table 17-5. 17.8.3 ADC prescaler selection.
AT90PWM81/161 In case of trig on PSCnASY event, there is no flag. So, if ADSSEN is reset, a conversion will start each time the trig event appears and the previous conversion is completed. Table 17-6. 17.8.4 ADC auto trigger source selection.
AT90PWM81/161 17.8.4.2 ADLAR = 1 Bit 17.8.
AT90PWM81/161 Amplified conversions can be synchronized to PSC events (see “Synchronization source description in one/two/four ramp modes.” on page 134 and “Synchronization source description in centered mode.” on page 135) or to the internal clock CKADC equal to eighth the ADC clock frequency. In case the synchronization is done by the ADC clock divided by eight, this synchronization is done automatically by the ADC interface in such a way that the sample-and-hold occurs at a specific phase of CKADC2.
AT90PWM81/161 Figure 17-15. Amplifier synchronization timing diagram with change on analog input signal. Delta V 4th stable sample Signal to be measured PSC Block PSCn_ASY AMPLI_clk (Sync Clock) CK ADC Ampli er Block Ampli er Sample Enable Ampli er Hold Value Valid sample ADSC ADC ADC Activity ADC Conv ADC Conv ADC Sampling ADC Sampling ADC Result Ready ADC Resu Ready Figure 17-16. Amplifier synchronization timing diagram: behavior when ADSC is set when the amplifier output is changing.
AT90PWM81/161 The block diagram of the two amplifiers is shown on Figure 17-17. Figure 17-17. Amplifiers block diagram. + SAMPLING AMP0+ AMP0- Toward ADC MUX (AMP0) - ADCK/8 PSCRASY 00 01 10 11 Sampling Clock PSC2ASY no short AMP0+ GND AMP0EN AMP0IS AMP0G1 AMP0G0 AMP0GS - AMP0TS1 AMP0TS0 AMP0CSR If APMP0GS bit is set, the AMP0- input is open and PD5/AMP0- pin is free for another use. At the same time the negative input of the Amplifier is internally grounded. 17.
AT90PWM81/161 • Bit 5, 4– AMP0G1, 0: Amplifier 0 Gain Selection Bits These two bits determine the gain of the amplifier 0. The different setting are shown in Table 17-7. Table 17-7. Amplifier 0 gain selection. AMP0G1 AMP0G0 Description 0 0 Gain 5 0 1 Gain 10 1 0 Gain 20 1 1 Gain 40 To ensure an accurate result, after the gain value has been changed, the amplifier input needs to have a quite stable input value during at least four Amplifier synchronization clock periods.
AT90PWM81/161 18. Digital to Analog Converter - DAC 18.1 Features • • • • • 10 bits resolution 8 bits linearity ±0.5LSB accuracy between 100mV and AVCC - 100mV VOUT = DAC × VREF/1023 The DAC could be connected to the negative inputs of the analog comparators The AT90PWM81/161 features a 10-bit Digital to Analog Converter. This DAC can be used for the analog comparators. The DAC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than ±0.3V from VCC.
AT90PWM81/161 18.2 Operation The Digital to Analog Converter generates an analog signal proportional to the value of the DAC registers value. In order to have an accurate sampling frequency control, there is the possibility to update the DAC input values through different trigger events. 18.3 Starting a Conversion The DAC is configured thanks to the DACON register.
AT90PWM81/161 • Bit 7 – DAATE: DAC Auto Trigger Enable bit (not useful, may be left for compatibility) Set this bit to update the DAC input value on the positive edge of the trigger signal selected with the DACTS2-0 bit in DACON register. Clear it to automatically update the DAC input when a value is written on DACH register. • Bit 6:4 – DATS2, DATS1, DATS0: DAC Trigger Selection bits (not useful, may be left for compatibility) These bits are only necessary in case the DAC works in auto trigger mode.
AT90PWM81/161 18.4.2.
AT90PWM81/161 19. debugWIRE On-chip Debug System 19.1 Features • • • • • • • • • • 19.
AT90PWM81/161 • Pull-up resistors on the dW/(RESET) line must not be smaller than 10kW. The pull-up resistor is not required for debugWIRE functionality • Connecting the RESET pin directly to VCC will not work • Capacitors connected to the RESET pin must be disconnected when using debugWire • All external reset sources must be disconnected 19.4 Software Break Points The debugWIRE supports Program memory Break Points by the AVR Break instruction.
AT90PWM81/161 20. Boot Loader Support – Read-While-Write Self-Programming In AT90PWM81/161, the Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program.
AT90PWM81/161 sections that are configured by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-WhileWrite (NRWW) section. The limit between the RWW- and NRWW sections is given in Table 209 on page 247 and Figure 20-2 on page 236.
AT90PWM81/161 Figure 20-1. Read-while-write vs. no read-while-write.
AT90PWM81/161 Figure 20-2. Memory sections.
AT90PWM81/161 Boot Lock Bit0 protection modes (application section) (1). Table 20-2. BLB0 mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
AT90PWM81/161 20.5.1 SPMCSR - Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
AT90PWM81/161 • Bit 2 – PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles.
AT90PWM81/161 Figure 20-3. Addressing the flash during SPM (1). BIT 15 ZPCMSB ZPAGEMSB Z - REGISTER 1 0 0 PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Note: 20.7 1. The different variables used in Figure 20-3 are listed in Table 20-10 on page 247. Self-Programming the Flash The program memory is updated in a page by page fashion.
AT90PWM81/161 20.7.1 Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation.
AT90PWM81/161 completed, the user software must clear the RWWSB by writing the RWWSRE. See “Simple Assembly Code Example for a Boot Loader” on page 245 for an example. 20.7.7 Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR.
AT90PWM81/161 the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below. Refer to Table 21-5 on page 250 for detailed description and mapping of the Fuse High byte. Bit 7 6 5 4 3 2 1 0 Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0 When reading the Extended Fuse byte, load 0x0002 in the Z-pointer.
AT90PWM81/161 Table 20-5. Signature row addressing. (Continued) Signature Byte Final test amb VREF: HIGH BYTE (3) Final test hot VREF: LOW BYTE (only a Read) (4) Final test hot VREF: HIGH BYTE (only a Read) Note: (5) Address AT90PWM81 data AT90PWM161 data 0x3D XXH XXH 0x3E XXH XXH 0x3F XXH XXH 1. TSGAIN typical value is 0x80=128 2. See Note 3 3. Final Test Amb VREF HIGH BYTE and LOW BYTE: Typical values are for VREF = 2.
AT90PWM81/161 20.7.13 Simple Assembly Code Example for a Boot Loader ;-the routine writes one page of data from RAM to Flash ; the first data location in RAM is pointed to by the Y pointer ; the first data location in Flash is pointed to by the Z-pointer ;-error handling is not included ;-the routine must be placed inside the Boot space ; (at least the Do_spm sub routine). Only code inside NRWW section can ; be read during Self-Programming (Page Erase and Page Write).
AT90PWM81/161 ; return to RWW section ; verify that RWW section is safe to read Return: in temp1, SPMCSR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable the RWW section ldi spmcrval, (1<
AT90PWM81/161 For AT90PWM161. Table 20-8. Boot size configuration.
AT90PWM81/161 21. Memory Programming 21.1 Program And Data Memory Lock Bits The AT90PWM81/161 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 21-2. The Lock bits can only be erased to “1” with the Chip Erase command. Table 21-1.
AT90PWM81/161 Table 21-3. Lock bit protection modes (1)(2). Only ATmega88/168. BLB0 mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 3 0 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
AT90PWM81/161 PSCRV gives the state low or high which will be forced on PSC outputs selected by PSC0RB & PSC2RB fuses. If PSCRV fuse equals 0 (programmed), the selected PSC outputs will be forced to low state. If PSCRV fuse equals 1 (unprogrammed), the selected PSC outputs will be forced to high state. If PSCRRB fuse equals 1 (unprogrammed), PSCOUTR0 & PSCOUTR1 keep a standard port behavior.
AT90PWM81/161 Table 21-6. Fuse Low byte. Low Fuse byte Bit no.
AT90PWM81/161 21.4 Calibration Byte The AT90PWM81/161 has a byte calibration value for the internal RC Oscillator. This byte resides in the byte of address 0x003 in the signature address space. During reset, this byte is automatically written into the OSCCAL Register to ensure correct frequency of the calibrated RC Oscillator. 21.
AT90PWM81/161 Table 21-8. Pin name mapping. (Continued) Signal name in programming mode Pin name I/O XA1/BS2 PD6 I XTAL Action Bit 1 Byte Select 2 (“0” selects Low byte, “1” selects 2’nd High byte) PAGEL/BS1 PE2 I Program memory and EEPROM Data Page Load Byte Select 1 (“0” selects Low byte, “1” selects High byte) DATA PB[7:0] I/O Table 21-9. Function Bi-directional Data bus (Output when OE is low) Pin Values Used to Enter Programming Mode.
AT90PWM81/161 Table 21-12. No. of words in a page and no. of pages in the flash. Device Flash size Page size PCWORD No. of pages PCPAGE PCMSB AT90PWM81 4K words (8Kbytes) 32 words PC[4:0] 128 PC[11:5] 11 AT90PWM161 8K words (16Kbytes) 64 words PC[5:0] 128 PC[12:6] 12 Table 21-13. No. of words in a page and no. of pages in the EEPROM. 21.6 Device EEPROM size Page size PCWORD No.
AT90PWM81/161 5. Wait until VCC actually reaches 4.5V -5.5V before giving any parallel programming commands. 6. Exit Programming mode by power the device down or by bringing RESET pin to 0V. 21.7.2 Considerations for Efficient Programming The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered.
AT90PWM81/161 1. Set XA1, XA0 to “01”. This enables data loading. 2. Set DATA = Data low byte (0x00 - 0xFF). 3. Give XTAL1 a positive pulse. This loads the data byte. D. Load Data High Byte 1. Set BS1 to “1”. This selects high data byte. 2. Set XA1, XA0 to “01”. This enables data loading. 3. Set DATA = Data high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the data byte. E. Latch Data 1. Set BS1 to “1”. This selects high data byte. 2. Give PAGEL a positive pulse.
AT90PWM81/161 Figure 21-2. Addressing the flash, which is organized in pages (1). PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Note: 1. PCPAGE and PCWORD are listed in Table 21-12 on page 254. Figure 21-3. Programming the flash waveforms (1). F DATA A B 0x10 ADDR. LOW C DATA LOW D DATA HIGH E XX B ADDR. LOW C D DATA LOW DATA HIGH E XX G ADDR.
AT90PWM81/161 L: Program EEPROM page 1. Set BS1 to “0”. 2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low. 3. Wait until to RDY/BSY goes high before programming the next page (see Figure 21-4 for signal waveforms). Figure 21-4. Programming the EEPROM waveforms. K DATA A G 0x11 ADDR. HIGH B ADDR. LOW C DATA E XX B ADDR. LOW C DATA E L XX XA1/BS2 XA0 PAGEL/BS1 XTAL1 WR RDY/BSY RESET +12V OE 21.7.
AT90PWM81/161 21.7.9 Programming the Fuse High Bits The algorithm for programming the Fuse High bits is as follows (refer to “Programming the Flash” on page 255 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS1 to “1” and BS2 to “0”. This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS1 to “0”. This selects low data byte. 21.7.
AT90PWM81/161 21.7.12 Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash” on page 255 for details on Command loading): 1. A: Load Command “0000 0100”. 2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can now be read at DATA (“0” means programmed). 3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can now be read at DATA (“0” means programmed). 4.
AT90PWM81/161 21.8 Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 21-14 on page 254, the pin mapping for SPI programming is listed.
AT90PWM81/161 case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”. 2. Wait for at least 20ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction.
AT90PWM81/161 Table 21-15. Minimum wait delay before writing the next flash or EEPROM location. Symbol Minimum wait delay tWD_FLASH 4.5ms tWD_EEPROM 3.6ms tWD_ERASE 9.0ms Figure 21-8. Serial programming waveforms. SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE Table 21-16. Serial programming instruction set.
AT90PWM81/161 Table 21-16. Serial programming instruction set. (Continued) Instruction format Instruction Byte 1 Byte 2 Byte 3 Byte 4 Operation 1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock bits. Set bits = “0” to program Lock bits. See Table 21-1 on page 248 for details 0011 0000 000x xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b 1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to unprogram.
AT90PWM81/161 22. Electrical Characteristics (1) 22.1 Absolute Maximum Ratings* Operating temperature................................... -40°C to +105°C Or operating temperature .............................. -40°C to +125°C Storage temperature...................................... -65°C to +150°C Voltage on any pin except RESET with respect to ground .................................-1.0V to VCC+0.5V Voltage on RESET with respect to ground ......-1.0V to +13.
AT90PWM81/161 22.2 DC Characteristics TA = -40°C to +105°C, VCC = 2.7V to 5.5V (unless otherwise noted). Symbol Parameter Condition VIL Input low voltage Port B & D and XTAL1, XTAL2 pins as I/O VIH Input high voltage VIL1 Minimum Typical Maximum -0.5 0.2VCC (1) Port B D and XTAL1, XTAL2 pins as I/O 0.6VCC (2) VCC+0.5 Input low voltage XTAL1 pin , External Clock Selected -0.5 0.1VCC (1) VIH1 Input high voltage XTAL1 pin , External Clock Selected 0.7VCC (2) VCC+0.
AT90PWM81/161 TA = -40°C to +105°C, VCC = 2.7V to 5.5V (unless otherwise noted). (Continued) Symbol Parameter Condition Minimum Typical Maximum Active 8MHz, VCC = 3V, RC osc., PRR = 0xFF 3.5 5 Active 16MHz, VCC = 5V, Ext Clock, PRR = 0xFF 10.5 15 Idle 8MHz, VCC = 3V, RC Osc 1.5 2 Idle 16MHz, VCC = 5V, Ext Clock 4.5 7 Power supply current mA WDT enabled,VCC = 3V 25°C 7 WDT enabled, VCC = 3V 105°C ICC 10 WDT enabled, VCC = 5V 105°C 0.
AT90PWM81/161 TA = -40°C to +125°C, VCC = 2.7V to 5.5V (unless otherwise noted). (Continued) Symbol Parameter Condition VIL Input low voltage Port B & D and XTAL1, XTAL2 pins as I/O VIH Input high voltage Port B D and XTAL1, XTAL2 pins as I/O VIL1 Input low voltage VIH1 Minimum Typical Maximum -0.5 0.2VCC (1) 0.6VCC (2) VCC+0.5 XTAL1 pin, External Clock selected -0.5 0.1VCC (1) Input high voltage XTAL1 pin, External Clock selected 0.7VCC (2) VCC+0.
AT90PWM81/161 Symbol Parameter Condition Minimum Typical Maximum Active 8MHz, VCC = 3V, RC osc, PRR = 0xFF 3.5 5 Active 16MHz, VCC = 5V, Ext Clock, PRR = 0xFF 10.5 15 Idle 8MHz, VCC = 3V, RC Osc 1.5 2 Idle 16MHz, VCC = 5V, Ext Clock 4.5 7 Power supply current mA WDT enabled, VCC = 3V 25°C 7 WDT enabled, VCC = 3V 125°C ICC 70 WDT enabled, VCC = 5V 25°C Power-down mode (5) 10 WDT enabled, VCC = 5V 125°C 110 µA WDT disabled, VCC = 3V 25°C 0.
AT90PWM81/161 If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: SO20 and TQFN Package: 1] The sum of all IOH, for all ports, should not exceed 400mA.
AT90PWM81/161 22.3.4 External Clock Drive Table 22-3. External clock drive. VCC = 2.7V - 5.5V 22.4 Symbol Parameter 1/tCLCL VCC = 4.5V - 5.5V Minimum Maximum Minimum Maximum Units Oscillator frequency 0 12 0 16 MHz tCLCL Clock period 83 62 tCHCX High time 30 20 tCLCX Low time 30 20 tCLCH Rise time 1.6 0.5 tCHCL Fall time 1.6 0.5 DtCLCL Change in period from one clock cycle to the next 2 2 ns ms % Maximum Speed vs. VCC Maximum frequency is depending on VCC.
AT90PWM81/161 Notes: 1. While connected to external clock or external oscillator, PLL Input Frequency must be selected to provide outputs with frequency in accordance with driven parts of the circuit. 2. When VCC is below 4.5V, maximum PLLF is 6. 22.6 SPI Timing Characteristics See Figure 22-3 on page 273 and Figure 22-4 on page 273 for details. Table 22-5. SPI timing parameters.
AT90PWM81/161 Figure 22-3. SPI interface timing requirements (Master mode). SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 MSB ... LSB 7 MOSI (Data Output) MSB 8 ... LSB Figure 22-4. SPI interface timing requirements (Slave mode). SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) MSB 17 ...
AT90PWM81/161 22.7 ADC Characteristics Table 22-6. Symbol ADC characteristics - TA = -45°C to +105°C, VCC = 2.7V to 5.5V (unless otherwise noted). Parameter Resolution Absolute accuracy Integral non-linearity Condition Minimum Typical Maximum Single Ended Conversion 10 Differential conversion, Gain = 5× or 10× 8 Differential conversion, Gain = 20× or 40× 8 Single Ended Conversion, VCC = 4V, VREF = 4V ADC clock = 1MHz 2 4 Single Ended Conversion, VCC = 2.7V, VREF =2.
AT90PWM81/161 Table 22-6. Symbol ADC characteristics - TA = -45°C to +105°C, VCC = 2.7V to 5.5V (unless otherwise noted). (Continued) Parameter Differential non-linearity Gain error Offset error Conversion time Condition Typical Maximum Single Ended conversion, VCC = 4V, VREF = 4V ADC clock = 1MHz 0.2 0.5 Single Ended conversion, VCC = 4V, VREF = 4V ADC clock = 2MHz 0.6 1 Single Ended conversion, VCC = 2.7V, VREF =2.56V ADC clock = 2MHz 1.0 2.
AT90PWM81/161 Table 22-6. Symbol ADC characteristics - TA = -45°C to +105°C, VCC = 2.7V to 5.5V (unless otherwise noted). (Continued) Parameter Condition Minimum Typical RREF Reference input resistance 30 RAIN Analog input resistance 23 CAIN Analog input capacitor 10 IHSM Increased current consumption 22.8 High speed mode Single Ended conversion pF 380 µA DAC Characteristics Symbol 22.9 Units kW Table 22-7. VREF Maximum DAC characteristics - TA = -45°C to +105°C, VCC = 2.7V to 5.
AT90PWM81/161 Figure 22-6. Parallel programming timing, loading sequence with timing requirements (1). LOAD ADDRESS (LOW BYTE) LOAD DATA (LOW BYTE) LOAD DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) t XLXH XTAL1 PAGEL/BS1 DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1/BS2 Note: 1. The timing requirements shown in Figure 22-5 on page 276 (that is, tDVXH, tXHXL, and tXLDX) also apply to loading operation. Figure 22-7.
AT90PWM81/161 Parallel programming characteristics, VCC = 5V ±10%. Table 22-8.
AT90PWM81/161 23. AT90PWM81/161 Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR register set and thus, the corresponding I/O modules are turned off.
AT90PWM81/161 23.1 Active Supply Current Figure 23-1. Active supply current vs. frequency (0.1MHz - 1.0MHz). ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY 1.2 5.5V 1 5.0V 4.5V ICC [mA] 0.8 4.0V 0.6 3.6V 3.3V 0.4 2.7V 0.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
AT90PWM81/161 Figure 23-2. Active supply current vs. frequency (1MHz - 16MHz). ACTIVE SUPPLY CURRENT vs. FREQUENCY 14 12 5.5V 10 5.0V 4.5V ICC [mA] 8 6 4.0V 3.6V 4 2.7V 3.3V 2 0 1 3 5 7 9 11 13 15 Frequency [MHz] Figure 23-3. Active supply current vs. VCC (internal RC oscillator, 8MHz). ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8MHz E AT 10 9 8 7 T ICC [mA] 6 PL TE M C TE RA A CH E OB ZE RI D 125°C 105°C 25°C -40°C 5 4 3 2 1 0 2.7 3.2 3.7 4.2 4.7 5.
AT90PWM81/161 Figure 23-4. Active supply current vs. VCC (external clock, 16MHz). ACTIVE SUPPLY CURRENT vs. VCC EXTERNAL CLOCK 16MHz - ATD ON 16 14 125°C 105°C 25°C -40°C 12 ICC [mA] 10 8 6 4 2 0 2.7 3.2 3.7 4.2 4.7 5.2 VCC [V] 23.2 Idle Supply Current Figure 23-5. Idle supply current vs. frequency (0.1MHz - 1.0MHz). IDLE SUPPLY CURRENT vs. LOW FREQUENCY 0.35 5.5V 0.3 5.0V ICC [mA] 0.25 4.5V 0.2 4.0V 0.15 3.6V 3.3V 2.7V 0.1 0.05 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
AT90PWM81/161 Figure 23-6. Idle supply current vs. frequency (1MHz - 16MHz). IDLE SUPPLY CURRENT vs. FREQUENCY 5 5.5V 4.5 5.0V 4 4.5V 3.5 4.0V ICC [mA] 3 3.6V 2.5 3.3V 2 2.7V 1.5 1 0.5 0 1 3 5 7 9 Frequency [MHz] 11 13 15 Figure 23-7. Idle supply current vs. VCC (internal RC oscillator, 8MHz). IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8MHz 4 3.5 125°C 3 105°C 2.5 -40°C ICC [mA] 25°C 2 1.5 1 0.5 0 2.7 3.2 3.7 4.2 VCC [V] 4.7 5.
AT90PWM81/161 Figure 23-8. Idle supply current vs. VCC (external clock, 16MHz). IDLE SUPPLY CURRENT vs. VCC EXTERNAL CLOCK 16MHz 6 -40°C 125°C 105°C 25°C 5 ICC [mA] 4 3 2 1 0 2.7 23.3 3.2 3.7 4.2 VCC [V] 4.7 5.2 Power-Down Supply Current Figure 23-9. Power-down supply current vs. VCC (watchdog timer disabled). POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 12 10 125°C ICC [µA] 8 6 4 105°C 2 25°C 0 2.7 3.2 3.7 4.2 4.7 5.
AT90PWM81/161 Figure 23-10. Power-down supply current vs. VCC (watchdog timer enabled). POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER ENABLED 25 20 125°C ICC [µA] 15 105°C 10 -40°C 25°C 5 0 2.7 3.2 3.7 4.2 4.7 5.2 VCC [V] 23.4 Pin Pull-up Figure 23-11. I/O pin pull-up resistor current vs. input voltage (VCC = 5V). I/O PIN PULL-UP RESISTOR CURRENT vs.
AT90PWM81/161 Figure 23-12. I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V). I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7V 80 25°C -40°C 70 105°C 125°C 60 IOP [µA] 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 VOP [V] 3 3.5 4 4.5 5 Figure 23-13. I/O pin pull-up resistor current vs. input voltage, PE1 & PE2 pins (VCC = 5V). I/O PIN PULL-UP RESISTOR CURRENT vs.
AT90PWM81/161 Figure 23-14. I/O pin pull-up resistor current vs. input voltage, PE1 & PE2 pins (VCC = 2.7V). I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE PE1 & PE2 PINS Vcc = 2.7V 90 80 -40°C 105°C 25°C 70 125°C IOP [µA] 60 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP [V] Figure 23-15. Reset pull-up resistor current vs. reset pin voltage (VCC = 5V). RESET PULL-UP RESISTOR CURRENT vs.
AT90PWM81/161 Figure 23-16. Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V). RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 2.7V 60 -40°C 105°C 25°C 50 125°C IRESET [µA] 40 30 20 10 0 0 23.5 0.5 1 1.5 2 2.5 VRESET [V] 3 3.5 4 4.5 5 Pin output high voltage Figure 23-17. I/O pin output voltage vs. source current (VCC = 5V). I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT Vcc = 5.
AT90PWM81/161 Figure 23-18. I/O pin output voltage vs. source current (VCC = 3V). I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT Vcc = 3.0V 3.5 3 -40°C 25°C 105°C 125°C VOH [V] 2.5 2 1.5 1 0.5 0 0 23.6 1 2 3 4 5 IOH [mA] 6 7 8 9 10 Pin output low voltage Figure 23-19. I/O pin output voltage vs. sink current (VCC = 5V). I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT Vcc = 5.0V 0.6 0.5 125°C 105°C VOL [V] 0.4 25°C 0.3 -40°C 0.2 0.
AT90PWM81/161 Figure 23-20. I/O pin output voltage vs. sink current (VCC = 3V). I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT Vcc = 3.0V 0.8 125°C 105°C 0.7 VOL [V] 0.6 0.5 25°C 0.4 -40°C 0.3 0.2 0.1 0 0 23.7 1 2 3 4 5 IOL [mA] 6 7 8 9 10 Pin Thresholds Figure 23-21. I/O pin input threshold voltage vs. VCC (VIL, I/O pin read As '0'). I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 3 125°C 2.5 -40°C 105°C 25°C Threshold [V] 2 1.5 1 0.5 0 2.7 3.2 3.7 4.2 V CC [V] 4.
AT90PWM81/161 Figure 23-22. I/O pin input threshold voltage vs. VCC (VIH, I/O pin read as '1'). I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 4 3.5 125°C 105°C Threshold [V] 3 -40°C 2.5 25°C 2 1.5 1 0.5 0 2.7 23.8 3.2 3.7 4.2 V CC [V] 4.7 5.2 BOD Thresholds Figure 23-23. BOD thresholds vs. temperature (BODLEVEL is 4.3V). BOD THRESHOLDS vs. TEMPERATURE BODLEVEL is 4.3V 4.6 Rising Vcc 4.5 4.4 Threshold [V] Falling Vcc 4.3 4.2 4.1 4 3.9 3.
AT90PWM81/161 Figure 23-24. BOD thresholds vs. temperature (BODLEVEL is 2.7V). BOD THRESHOLDS vs. TEMPERATURE BODLEVEL is 2.7V 2.9 Rising Vcc Threshold [V] 2.8 Falling Vcc 2.7 2.6 2.5 2.4 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature [°C] 23.9 Analog Reference Figure 23-25. VREF voltage vs. VCC. IINTERNAL VREF vs Vcc 2.65 125°C 105°C 2.6 25°C VRef (V) 2.55 2.5 2.45 -40°C 2.4 2.35 2.3 2.7 3.2 3.7 4.2 4.7 5.
AT90PWM81/161 Figure 23-26. VREF voltage vs. temperature. INTERNAL VREF vs TEMPERATURE 2.65 5.5V 2.6 2.7V Aref (V) 2.55 2.5 2.45 2.4 2.35 -40 -30 -20 -10 0 10 20 30 40 50 60 Temperature (°C) 70 80 90 100 110 120 23.10 Internal Oscillator Speed Figure 23-27. Watchdog oscillator frequency vs. VCC. WATCHDOG OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 0.14 0.135 0.13 -40°C FRC [MHz] 0.125 25°C 0.12 125°C 0.115 105°C 0.11 0.105 0.1 2.7 3.2 3.7 4.2 4.7 5.
AT90PWM81/161 Figure 23-28. Calibrated 8MHz RC oscillator frequency vs. temperature. CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE RC OSC CALIBRATED @ ROOM TEMP 8.3 5.6V 5.4V 5.2V 5V4V 2.6V 2.8V 8.2 FRC [MHz] 8.1 V 8 7.9 7.8 7.7 -40 -25 -10 5 20 35 50 Temperature [°C] 65 80 95 110 125 Figure 23-29. Calibrated 8MHz RC oscillator frequency vs. VCC. CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE RC OSC CALIBRATED @ ROOM TEMP 8.3 125°C 105°C 8.2 FRC [MHz] 8.
AT90PWM81/161 Figure 23-30. Calibrated 8MHz RC oscillator frequency vs. osccal value. INT RC OSCILLATOR Frequency vs. OSCCAL 10000 Cycles sampled with 250nS - VCC 3V 105°C 25°C 1600000 -40°C 1400000 FRC 1200000 1000000 800000 600000 400000 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL 23.11 Current Consumption in Reset Figure 23-31. Reset supply current vs. VCC (0.1MHz - 1.0MHz, excluding current through the reset pull-up).
AT90PWM81/161 Figure 23-32. Reset supply current vs. VCC (1MHz - 16MHz, excluding current through the reset pull-up). 4 3.5 3 5.5V ICC (mA) 2.5 2 1.5 1 2.7V 0.
AT90PWM81/161 24.
AT90PWM81/161 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xBF) Reserved – – – – – – – – Page (0xBE) Reserved – – – – – – – – (0xBD) Reserved – – – – – – – – (0xBC) Reserved – – – – – – – – (0xBB) Reserved – – – – – – – – (0xBA) Reserved – – – – – – – – (0xB9) Reserved – – – – – – – – (0xB8) Reserved – – – – – – – – (0xB7) Reserved – – – – – – – – (0xB6) Reserved – – – – – – – – (
AT90PWM81/161 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x7D) AC1CON AC1EN AC1IE AC1IS1 AC1IS0 – AC1M2 AC1M1 AC1M0 197 (0x7C) AC3ECON – – AC3OI AC3OE – AC3H2 AC3H1 AC3H0 200 (0x7B) AC2ECON – – AC2OI AC2OE – AC2H2 AC2H1 AC2H0 200 (0x7A) AC1ECON – – AC1OI AC1OE AC1ICE AC1H2 AC1H1 AC1H0 200 (0x79) AMP0CSR AMP0EN AMP0IS AMP0G1 AMP0G0 (0x78) DIDR1 – – – – (0x77) DIDR0 ADC8D/ACMP3D (0x76) DACON DAATE ADC7D/AMP0-D DA
AT90PWM81/161 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x1B (0x3B) GPIOR2 GPIOR27 GPIOR26 GPIOR25 GPIOR24 GPIOR23 GPIOR22 GPIOR21 GPIOR20 26 0x1A (0x3A) GPIOR1 GPIOR17 GPIOR16 GPIOR15 GPIOR14 GPIOR13 GPIOR12 GPIOR11 GPIOR10 26 0x19 (0x39) GPIOR0 GPIOR07 GPIOR06 GPIOR05 GPIOR04 GPIOR03 GPIOR02 GPIOR01 GPIOR00 26 0x18 (0x38) SPSR SPIF WCOL – – – – – SPI2X 188 0x17 (0x37) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 186 0
AT90PWM81/161 25.
AT90PWM81/161 Mnemonics Operands Description Operation Flags #Clocks BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ¬ PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ¬ PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ¬ PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ¬ 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ¬ 0 None 2 LSL Rd Logical Shift Left Rd(
AT90PWM81/161 Mnemonics Operands Description Operation Flags PUSH Rr Push Register on Stack STACK ¬ Rr None #Clocks 2 POP Rd Pop Register from Stack Rd ¬ STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr.
AT90PWM81/161 26. Ordering Information Speed (MHz) 16 16 Power supply 2.7V - 5.5V 2.7V - 5.
AT90PWM81/161 26.
AT90PWM81/161 26.
AT90PWM81/161 27. Errata 27.1 Errata AT90PWM81 revA • 27.2 Available on request Errata AT90PWM81 revB • Clock Switch disable • Crystal oscillator control with Clock Switch • BOD disable fuse • PSC output at reset • Flash and EEPROM programming failure if CPU clock is switched • ADC AMPlifier measurement is unstable • ADC measurement reports abnormal values with PSC2-synchronized conversions • Over-consumption in power down sleep mode 1.
AT90PWM81/161 5. Flash and EEPROM programming failure if CPU clock is switched If Clock switching is used in the Application, the memory programming is only possible when the internal RC oscillator is selected as System clock. If the Application requires a memory programming on a clock source different from the internal RC oscillator, do not switch to this clock source. Work around: - Use internal RC oscillator when programming Flash and EEPROM, or - Do not use clock switching. 6.
AT90PWM81/161 1. Clock Switch enable & disable After a “Enable Clock Source” or a “Disable Clock Source” command, the command is still active until the next access of CLKCSR register. If CLKSEL is written with a new value, the corresponding clock will be unintentionnaly enabled or disabled. Work around: Atter the Enable or Disable command, write CLKCSR with value 1<
AT90PWM81/161 7. ADC measurement reports abnormal values with PSC2-synchronized conversions When using ADC in synchronized mode, an unexpected extra Single ended conversion can spuriously re-start.This can occur when the End of conversion and the Trigger event occur at the same time. Work around: No workaround 8. Over-consumption in power down sleep mode. In Power-down mode, an extra power consumption up to 500µA may occur. Work around: No workaround 27.
AT90PWM81/161 4. Flash and EEPROM programming failure if CPU clock is switched If Clock switching is used in the Application, the memory programming is only possible when the internal RC oscillator is selected as System clock. If the Application requires a memory programming on a clock source different from the internal RC oscillator, do not switch to this clock source. Work around: - Use internal RC oscillator when programming Flash and EEPROM, or - Do not use clock switching 5.
AT90PWM81/161 2. Crystal oscillator control with Clock Switch When a Xtal oscillator is active and CLKSELR is written with a new value for the selection of another clock source (for instance RC or WD) , the Xtal oscillator gain is not correct. Work around: After the commands “Enable Clock Source” and “Clock Source Switching”, write back CLKSELR with the values corresponding to the active Xtal oscillator 3. BOD disable fuse It is strongly advised to keep the BOD active.
AT90PWM81/161 4. PSCRRB fuse When this Fuse bit is programmed in Parallel Programming mode, further parallel and ISP programming will not program the device correctly. Work around: Program the PSCRRB fuse using ISP mode. 5. Over-consumption in power down sleep mode In Power-down mode, an extra power consumption up to 500µA may occur. Work around: No workaround. 27.7 Errata AT90PWM161 revB • Clock Switch disable • Crystal oscillator control with Clock Switch • BOD disable fuse • PSCRRB fuse 1.
AT90PWM81/161 28. Datasheet Revision History for AT90PWM81/161 Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 28.1 Rev. 7734A 1. Document creation. 28.2 Rev. 7734B 1. GPIO3 suppressed for compatibility reason. 2. Pinout: PB7 & PD7 swapped. 3. CKSEL values redefined. 4. Clock switching & clock monitoring added. 5. PSCrOUT name changed to PSCOUTR. 6.
AT90PWM81/161 28.6 Rev. 7734F 1. Clean chapter clock from all “Power save”. 2. Update chapter “Calibrated Internal RC Oscillator” on page 29. 3. Update Table 7-9 on page 35: SUT for PLL. 4. Update chapter Idle Mode page 48. 5. Update figure “PSC Input Module A” on page 119 and “PSC Input Module B” on page 120. 6. Update figure “PSC behavior versus PSCn Input B in Mode 14” on page 132. 7.
AT90PWM81/161 5. Remove chapter 16.3 Band Gap calibration procedure on Page 191. 6. Update Temperature calibration on Page 191. 7. Remove chapter 16.4.3 Two Points Temperature sensor calibration on Page 197. 8. Update Signature Row Addressing on Page249. 9. Update DC Characteristics: Update table 23-1 Page 275: RC calibartion @25°C Update Table 23.2 page 272: -40°C in place of -45°C New Table in 23.2: -40°C to +125°C 10. Update Erratasheet. 28.10 Rev. 7734J 1. Page 2 Table 2-1: QFN32 : 32 Pins. 2.
AT90PWM81/161 28.16 Rev. 7734P 1. Updated “Electrical Characteristics (1)” on page 265 and “AT90PWM81/161 Typical Characteristics” on page 279. 28.17 Rev. 7734Q 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. General update and countless, small corrections. Table 8-1 on page 62 has been updated. The text in “Input Mode Operation” on page 160 has been updated. Changed the overlined text to normal text in the Note below Table 14-1 on page 182.
AT90PWM81/161 27. In chapter “PFRC0B - PSCR Input B Control Register” on page 175, in bullet point “Bit 3:0 – PRFM0x3:0: PSCR Fault Mode”, page 176, the text “PSCR Functional Specification” has been replaced by “Table 13-5 on page 160”. 28. In “Bit 2, 1, 0– AC3M2, AC3M1, AC3M0: Analog Comparator 3 Multiplexer register”, page 199, the reference “Table 16-4” has been corrected to “Table 16-6”. 29. In Table 21-5 on page 250, the reference “Table 113” has been corrected to “Table 20-7 on page 246” two places.
AT90PWM81/161 50. In “Features” on page 100, the text in one of the bullet pints has been corrected to “Abnormality protection function, emergency input to force all outputs to low level”. 51. @25°C has been removed several places in the table in “DC Characteristics” . 52. The rows describing 105°C on page 269 in the table in “DC Characteristics” have been removed. 53. The values in Table 7-2 on page 53 has been corrected. 54. The text below “Description” in Table 13-8 on page 171 has been corrected. 55.
AT90PWM81/161 Table Of Contents Features ..................................................................................................... 1 1 Products Configuration ........................................................................... 2 2 Pin Configurations ................................................................................... 3 2.1 3 4 5 6 Pin Descriptions .................................................................................................6 AVR CPU Core .......
AT90PWM81/161 7 8 6.6 Power Reduction Register ...............................................................................46 6.7 Minimizing Power Consumption ......................................................................47 6.8 Register description .........................................................................................48 System Control and Reset .................................................................... 50 7.1 System Control overview .........................
AT90PWM81/161 12.9 PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait .....121 12.10 PSC Input Mode 2: Stop signal, Execute Opposite Pulse and Wait ..............122 12.11 PSC Input Mode 3: Stop signal, Execute Opposite Pulse while Fault active 123 12.12 PSC Input Mode 4: Deactivate outputs without changing timing ...................124 12.13 PSC Input Mode 5: Stop signal and Insert Dead-Time ..................................124 12.
AT90PWM81/161 13.17 PSCR Input Mode 9: Fixed Frequency Edge Retrigger PSC ........................167 13.18 PSCR Input Mode 14: Fixed Frequency Edge Retrigger PSCR and Deactivate Output 168 13.19 Analog Synchronization .................................................................................169 13.20 Interrupt Handling ..........................................................................................169 13.21 PSC Clock Sources ........................................................
AT90PWM81/161 18 Digital to Analog Converter - DAC ..................................................... 227 18.1 Features ........................................................................................................227 18.2 Operation .......................................................................................................228 18.3 Starting a Conversion ....................................................................................228 18.4 DAC Register Description .......
AT90PWM81/161 22.6 SPI Timing Characteristics ............................................................................272 22.7 ADC Characteristics ......................................................................................274 22.8 DAC Characteristics ......................................................................................276 22.9 Parallel Programming Characteristics ...........................................................276 23 AT90PWM81/161 Typical Characteristics ..
AT90PWM81/161 28.5 Rev. 7734E ....................................................................................................314 28.6 Rev. 7734F ....................................................................................................315 28.7 Rev. 7734G ...................................................................................................315 28.8 Rev. 7734H ....................................................................................................315 28.9 Rev.
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1)(408) 441-0311 Fax: (+1)(408) 487-2600 www.atmel.com Atmel Asia Limited Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan 16F, Shin Osaki Kangyo Bldg.
