Datasheet

377
7682C–AUTO–04/08
AT90CAN32/64/128
Table 27-9. External Data Memory Characteristics, V
CC
= 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0
(1)
Symbol Parameter
8 MHz Oscillator Variable Oscillator
Unit
Min. Max. Min. Max.
0 1/t
CLCL
Oscillator Frequency 0.0 16 MHz
10 t
RLDV
Read Low to Data Valid 325 3.0 t
CLCL
– 50 ns
12 t
RLRH
RD Pulse Width 365 3.0 t
CLCL
– 10 ns
15 t
DVWH
Data Valid to WR High 375 3.0 t
CLCL
ns
16 t
WLWH
WR Pulse Width 365 3.0 t
CLCL
– 10 ns
Table 27-10. External Data Memory Characteristics, V
CC
= 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1
(1)
Symbol Parameter
8 MHz Oscillator Variable Oscillator
Unit
Min. Max. Min. Max.
0 1/t
CLCL
Oscillator Frequency 0.0 16 MHz
10 t
RLDV
Read Low to Data Valid 200 3.0 t
CLCL
– 50 ns
12 t
RLRH
RD Pulse Width 365 3.0 t
CLCL
– 10 ns
14 t
WHDX
Data Hold After WR High 240 2.0 t
CLCL
– 10 ns
15 t
DVWH
Data Valid to WR High 375 3.0 t
CLCL
ns
16 t
WLWH
WR Pulse Width 365 3.0 t
CLCL
– 10 ns
Table 27-11. External Data Memory Characteristics, V
CC
= 2.7 - 5.5 Volts, No Wait-state
(1)
Symbol Parameter
4 MHz Oscillator Variable Oscillator
Unit
Min. Max. Min. Max.
0 1/t
CLCL
Oscillator Frequency 0.0 16 MHz
1 t
LHLL
ALE Pulse Width 235 t
CLCL
– 15 ns
2 t
AVLL
Address Valid A to ALE Low 115 0.5 t
CLCL
– 10
(2)
ns
3a t
LLAX_ST
Address Hold After ALE Low,
write access
5 5 ns
3b t
LLAX_LD
Address Hold after ALE Low,
read access
5 5 ns
4 t
AVLLC
Address Valid C to ALE Low 115 0.5 t
CLCL
– 10
(2)
ns
5 t
AVRL
Address Valid to RD Low 235 1.0 t
CLCL
– 15 ns
6 t
AVWL
Address Valid to WR Low 235 1.0 t
CLCL
– 15 ns
7 t
LLWL
ALE Low to WR Low 115 130 0.5 t
CLCL
– 10
(3)
0.5 t
CLCL
+ 5
(3)
ns
8 t
LLRL
ALE Low to RD Low 115 130 0.5 t
CLCL
– 10
(3)
0.5 t
CLCL
+ 5
(3)
ns
9 t
DVRH
Data Setup to RD High 45 45 ns
10 t
RLDV
Read Low to Data Valid 190 1.0 t
CLCL
– 60 ns