Datasheet

180
7682C–AUTO–04/08
AT90CAN32/64/128
Note that fclk
io
depends on the stability of the system clock source. It is therefore recommended
to add some margin to avoid possible loss of data due to frequency variations.
17.4.4 Synchronous Clock Operation
When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input
(Slave) or clock output (Master). The dependency between the clock edges and data sampling
or data change is the same. The basic principle is that data input (on RxDn) is sampled at the
opposite XCKn clock edge of the edge the data output (TxDn) is changed.
Figure 17-3. Synchronous Mode XCKn Timing.
The UCPOLn bit UCRSnC selects which XCKn clock edge is used for data sampling and which
is used for data change. As
Figure 17-3 shows, when UCPOLn is zero the data will be changed
at rising XCKn edge and sampled at falling XCKn edge. If UCPOLn is set, the data will be
changed at falling XCKn edge and sampled at rising XCKn edge.
17.5 Serial Frame
A serial frame is defined to be one character of data bits with synchronization bits (start and stop
bits), and optionally a parity bit for error checking.
17.5.1 Frame Formats
The USARTn accepts all 30 combinations of the following as valid frame formats:
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even or odd parity bit
• 1 or 2 stop bits
A frame starts with the start bit followed by the least significant data bit. Then the next data bits,
up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit
is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can
be directly followed by a new frame, or the communication line can be set to an idle (high) state.
Figure 17-4 illustrates the possible combinations of the frame formats. Bits inside brackets are
optional.