Datasheet

109
7682C–AUTO–04/08
AT90CAN32/64/128
Figure 12-10 shows the setting of OCF0A in all modes except CTC mode.
Figure 12-10. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (f
clk_I/O
/8)
Figure 12-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode.
Figure 12-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
caler (f
clk_I/O
/8)
12.9 8-bit Timer/Counter Register Description
12.9.1 Timer/Counter0 Control Register A – TCCR0A
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode. However, for
ensuring compatibility with future devices, this bit must be set to zero when TCCR0A is written
when operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate com-
pare match is forced on the Waveform Generation unit. The OC0A output is changed according
to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a strobe. Therefore it is
the value present in the COM0A1:0 bits that determines the effect of the forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0A as TOP.
The FOC0A bit is always read as zero.
Bit 7 6 5 4 3 2 1 0
FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 TCCR0A
Read/Write W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0