Features • High-performance, Low-power AVR® 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • • • – 133 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers + Peripheral Control Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier Non volatile Program and Data Memories – 32K/64K/128K Bytes of In-System Reprogrammable Flash (AT90CAN32/64/128) • Endurance: 10,000 Write/Erase Cycles – Optional
1. Description 1.1 Comparison Between AT90CAN32, AT90CAN64 and AT90CAN128 AT90CAN32, AT90CAN64 and AT90CAN128 are all hardware and software compatible with each other, the only difference is the memory size. 1.2 Table 1-1.
AT90CAN32/64/128 combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel AT90CAN32/64/128 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The AT90CAN32/64/128 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 1.
Block Diagram PF7 - PF0 VCC PA7 - PA0 PC7 - PC0 PORTA DRIVERS PORTF DRIVERS RESET Block Diagram XTAL2 Figure 1-1. XTAL1 1.5 PORTC DRIVERS GND DATA DIR. REG. PORTF DATA REGISTER PORTF DATA DIR. REG. PORTA DATA REGISTER PORTA DATA REGISTER PORTC DATA DIR. REG.
AT90CAN32/64/128 Pin Configurations (1) GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4 / TCK) PF5 (ADC5 / TMS) PF6 (ADC6 / TDO) PF7 (ADC7 / TDI) GND VCC PA0 (AD0) PA1 (AD1) PA2 (AD2) 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinout AT90CAN32/64/128 - TQFP AVCC Figure 1-2. 64 1.
(1) AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4 / TCK) PF5 (ADC5 / TMS) PF6 (ADC6 / TDO) PF7 (ADC7 / TDI) GND VCC PA0 (AD0) PA1 (AD1) PA2 (AD2) 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinout AT90CAN32/64/128 - QFN 64 Figure 1-3.
AT90CAN32/64/128 1.7.3 Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running.
AT90CAN32/64/128 3. AVR CPU Core 3.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 3.2 Architectural Overview Figure 3-1.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
AT90CAN32/64/128 3.4 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
• Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 3.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
AT90CAN32/64/128 Figure 3-3. The X-, Y-, and Z-registers 15 X-register XH XL 7 0 R27 (0x1B) YH YL 7 0 R29 (0x1D) Z-register 0 R26 (0x1A) 15 Y-register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 ZL 7 R31 (0x1F) 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 3.5.
3.6 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer.
AT90CAN32/64/128 Figure 3-6 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 3-6. Single Cycle ALU Operation T1 T2 T3 T4 clk CPU Total Execution ime T Register Operands Fetch ALU Operation Execute Result rite W Back 3.8 Reset and Interrupt Handling The AVR provides several different interrupt sources.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.
AT90CAN32/64/128 3.8.2 Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles.
4. Memories This section describes the different memories in the AT90CAN32/64/128. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the AT90CAN32/64/128 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. Memory Mapping. Table 4-1.
AT90CAN32/64/128 Constant tables can be allocated within the entire program memory address space (see the LPM – Load Program Memory and ELPM – Extended Load Program Memory instruction description). Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 14. Figure 4-1. Program Memory Map Program Memory 0x0000 Application Flash Section Boot Flash Section Flash end 4.2 SRAM Data Memory Figure 4-2 shows how the AT90CAN32/64/128 SRAM Memory is organized.
4.2.1 SRAM Data Access When the addresses accessing the SRAM memory space exceeds the internal data memory locations, the external data SRAM is accessed using the same instructions as for the internal data memory access. When the internal data memories are accessed, the read and write strobe pins (PG0 and PG1) are inactive during the whole access cycle. External SRAM operation is enabled by setting the SRE bit in the XMCRA Register.
AT90CAN32/64/128 Figure 4-2. Data Memory Map Data Memory 32 Registers 0x0000 - 0x001F 0x0020 - 0x005F 64 I/O Registers 0x0060 - 0x00FF 160 Ext I/O Reg. ISRAM start Internal SRAM (ISRAM size) ISRAM end XMem start External SRAM (XMem size) 0xFFFF 4.2.2 SRAM Data Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 4-3. Figure 4-3.
4.3 EEPROM Data Memory The AT90CAN32/64/128 contains EEPROM memory (see “E2 size”). It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
AT90CAN32/64/128 4.3.3 The EEPROM Data Register – EEDR Bit 7 6 5 4 3 2 1 0 EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EEDR • Bits 7..0 – EEDR7.0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register.
Support – Read-While-Write Self-Programming” on page 320 for details about Boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.
AT90CAN32/64/128 The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
AT90CAN32/64/128 4.4 I/O Memory The I/O space definition of the AT90CAN32/64/128 is shown in “Register Summary” on page 384. All AT90CAN32/64/128 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
Figure 4-4. External Memory with Sector Select 0x0000 Internal memory ISRAM end XMem start Lower sector SRW01 SRW00 SRL[2..0] External Memory Upper sector (0-64K x 8) SRW11 SRW10 0xFFFF 4.5.2 Using the External Memory Interface The interface consists of: • AD7:0: Multiplexed low-order address bus and data bus. • A15:8: High-order address bus (configurable number of bits). • ALE: Address latch enable. • RD: Read strobe. • WR: Write strobe.
AT90CAN32/64/128 4.5.3 Address Latch Requirements Due to the high-speed operation of the XRAM interface, the address latch must be selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V. When operating at conditions above these frequencies, the typical old style 74HC series latch becomes inadequate. The External Memory Interface is designed in compliance to the 74AHC series latch. However, most latches can be used as long they comply with the main timing parameters.
address actually is driven on the bus. The access time cannot exceed the time from the ALE pulse must be asserted low until data is stable during a read sequence (see tLLRL+ tRLRH - tDVRH in Tables 26-7 through Tables 26-14). The different wait-states are set up in software. As an additional feature, it is possible to divide the external memory space in two sectors with individual wait-state settings.
AT90CAN32/64/128 Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal or external). Figure 4-8. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0(1) T1 T2 T3 T4 T5 T6 System Clock (CLKCPU ) ALE A15:8 Prev. addr. DA7:0 Prev. data Address DA7:0 (XMBK = 0) Prev. data Address DA7:0 (XMBK = 1) Prev.
4.5.6 External Memory Control Register A – XMCRA Bit 7 6 5 4 3 2 1 0 SRE SRL2 SRL1 SRL0 SRW11 SRW10 SRW01 SRW00 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 XMCRA • Bit 7 – SRE: External SRAM/XMEM Enable Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8, ALE, WR, and RD are activated as the alternate pin functions. The SRE bit overrides any pin direction settings in the respective data direction registers.
AT90CAN32/64/128 • Bit 3..2 – SRW11, SRW10: Wait-state Select Bits for Upper Sector The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the external memory address space, see Table 4-4. • Bit 1..0 – SRW01, SRW00: Wait-state Select Bits for Lower Sector The SRW01 and SRW00 bits control the number of wait-states for the lower sector of the external memory address space, see Table 4-4. Table 4-4.
Table 4-5. 4.5.8 Port C Pins Released as Normal Port Pins when the External Memory is Enabled XMM2 XMM1 XMM0 # Bits for External Memory Address Released Port Pins 0 0 0 8 (Full External Memory Space) None 0 0 1 7 PC7 0 1 0 6 PC7 .. PC6 0 1 1 5 PC7 .. PC5 1 0 0 4 PC7 .. PC4 1 0 1 3 PC7 .. PC3 1 1 0 2 PC7 ..
AT90CAN32/64/128 4.5.9 Using all 64KB Locations of External Memory Since the External Memory is mapped after the Internal Memory as shown in Figure 4-4, only (64K-(“ISRAM size”+256)) bytes of External Memory is available by default (address space 0x0000 to “ISRAM end” is reserved for internal memory). However, it is possible to take advantage of the entire External Memory by masking the higher address bits to zero.
4.6 General Purpose I/O Registers The AT90CAN32/64/128 contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags. The General Purpose I/O Register 0, within the address range 0x00 - 0x1F, is directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions. 4.6.
AT90CAN32/64/128 5. System Clock 5.1 Clock Systems and their Distribution Figure 5-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to unused modules can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 46. The clock systems are detailed below. Figure 5-1.
5.1.4 Asynchronous Timer Clock – clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. 5.1.5 ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry.
AT90CAN32/64/128 5.4 Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 5-2. Either a quartz crystal or a ceramic resonator may be used. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment.
Table 5-4. Start-up Times for the Oscillator Clock Selection CKSEL0 SUT1..0 Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) Recommended Usage 0 00 258 CK(1) 14 CK + 4.1 ms Ceramic resonator, fast rising power 0 01 258 CK(1) 14 CK + 65 ms Ceramic resonator, slowly rising power 0 10 1K CK(2) 14 CK Ceramic resonator, BOD enabled 0 11 1K CK(2) 14 CK + 4.
AT90CAN32/64/128 When this Oscillator is selected, start-up times are determined by the SUT1..0 fuses as shown in Table 5-5 and CKSEL1..0 fuses as shown in Table 5-6. Table 5-5. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection SUT1..0 Additional Delay from Reset (VCC = 5.0V) 00 14 CK 01 14 CK + 4.1 ms Slowly rising power 10 14 CK + 65 ms Stable frequency at start-up 11 Start-up Times for the Low-frequency Crystal Oscillator Clock Selection CKSEL3..
When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 5-8. Table 5-8. Start-up times for the internal calibrated RC Oscillator clock selection SUT1..0 Start-up Time from Powerdown and Power-save Additional Delay from Reset (VCC = 5.0V) 00 6 CK 14 CK 01 6 CK 14 CK + 4.1 ms Fast rising power 6 CK 14 CK + 65 ms Slowly rising power (1) 10 11 Note: 5.6.1 Recommended Usage BOD enabled Reserved 1. The device is shipped with this option selected.
AT90CAN32/64/128 Figure 5-4. External Clock Drive Configuration NC XTAL2 External Clock Signal XTAL1 GND Table 5-10. External Clock Frequency CKSEL3..0 Frequency Range 0000 0 - 16 MHz When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 5-11. Table 5-11. Start-up Times for the External Clock Selection SUT1..0 Start-up Time from Powerdown and Power-save Additional Delay from Reset (VCC = 5.0V) 00 6 CK 14 CK 01 6 CK 14 CK + 4.
AT90CAN32/64/128 share the Timer/Counter2 Oscillator Pins (TOSC1 and TOSC2) with PG4 and PG3. This means that both PG4 and PG3 can only be used when the Timer/Counter2 Oscillator is not enable. Applying an external clock source to TOSC1 can be done in asynchronous operation if EXTCLK in the ASSR Register is written to logic one. See “Asynchronous operation of the Timer/Counter2” on page 159 for further description on selecting external clock as input instead of a 32 kHz crystal.
AT90CAN32/64/128 “0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting.
6. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed.
AT90CAN32/64/128 purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. 6.1 Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, CAN, USART, Analog Comparator, ADC, Two-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating.
If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set, Timer/Counter2 will run during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2, and the global interrupt enable bit in SREG is set.
AT90CAN32/64/128 6.6.2 Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode.
this will contribute significantly to the total current consumption. There are three alternative ways to avoid this: • Disable OCDEN Fuse. • Disable JTAGEN Fuse. • Write one to the JTD bit in MCUCR. The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP controller is not shifting data. If the hardware connected to the TDO pin does not pull up the logic level, power consumption will increase.
AT90CAN32/64/128 7. System Control and Reset 7.1 7.1.1 Reset Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
Figure 7-1. Reset Logic DATA BUS MCU Status JTRF WDRF BORF Power-on Reset EXTRF PORF Register (MCUSR) Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor Spike Filter JTAG Reset Register Watchdog Oscillator Clock CK Delay Counters TIMEOUT Generator CKSEL[3:0] SUT[1:0] Table 7-1. Symbol Reset Characteristics Parameter Condition Min.
AT90CAN32/64/128 VCC rise. The RESET signal is activated again, without any delay, when VCC decreases below the detection level. Figure 7-2. MCU Start-up, RESET Tied to VCC V CCRR V CC V POR RESET V POT V CCRR tTOUT TIME-OUT INTERNAL RESET Figure 7-3. MCU Start-up, RESET Extended Externally V DDRR V CC V POR RESET V RST TIME-OUT tTOUT INTERNAL RESET Note: 7.1.4 If VPOR or VCCRR parameter range can not be followed, an External Reset is required.
Figure 7-4. External Reset During Operation CC 7.1.5 Brown-out Detection AT90CAN32/64/128 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V BOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2. Table 7-2.
AT90CAN32/64/128 When the BOD is enabled, and VCC decreases to a value below the trigger level (VBOT- in Figure 7-5), the Brown-out Reset is immediately activated. When VCC increases above the trigger level (V BOT+ in Figure 7-5), the delay counter starts the MCU after the Time-out period tTOUT has expired. The BOD circuit will only detect a drop in V CC if the voltage stays below the trigger level for longer than tBOD given in Table 7-1. Figure 7-5.
• Bit 7..5 – Reserved Bits These bits are reserved for future use. • Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.
AT90CAN32/64/128 7.2.2 Voltage Reference Characteristics Internal Voltage Reference Characteristics Table 7-4. Symbol 7.3 Parameter Condition Min. Typ. Max. Units 1.0 1.1 1.2 V 70 µs VBG Bandgap reference voltage tBG Bandgap reference start-up time 40 IBG Bandgap reference current consumption 15 µA Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is the typical value at VCC = 5V.
– – – WDCE WDE WDP2 WDP1 WDP0 Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 WDTCR • Bits 7..5 – Reserved Bits These bits are reserved bits for future use. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure.
AT90CAN32/64/128 The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
8. Interrupts This section describes the specifics of the interrupt handling as performed in AT90CAN32/64/128. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 15. 8.1 Interrupt Vectors in AT90CAN32/64/128 Table 8-1. 60 Reset and Interrupt Vectors Vector No.
AT90CAN32/64/128 Reset and Interrupt Vectors (Continued) Table 8-1. Vector No.
0x0012 jmp TIM2_COMP ; Timer2 Compare Handler 0x0014 jmp TIM2_OVF 0x0016 jmp TIM1_CAPT ; Timer1 Capture Handler 0x0018 jmp TIM1_COMPA; Timer1 CompareA Handler 0x001A jmp TIM1_COMPB; Timer1 CompareB Handler 0x001C jmp TIM1_OVF ; Timer1 CompareC Handler 0x001E jmp TIM1_OVF ; Timer1 Overflow Handler 0x0020 jmp TIM0_COMP ; Timer0 Compare Handler 0x0022 jmp TIM0_OVF 0x0024 jmp CAN_IT ; CAN Handler 0x0026 jmp CTIM_OVF ; CAN Timer Overflow Handler 0x0028 jmp SPI_STC ; SPI Tr
AT90CAN32/64/128 0x0004 sei ; Enable interrupts 0x0005 xxx ; .org (BootResetAdd + 0x0002) 0x..02 jmp EXT_INT0 ; IRQ0 Handler 0x..04 jmp PCINT0 ; PCINT0 Handler ... ... ... ; 0x..0C jmp SPM_RDY ; Store Program Memory Ready Handler When the BOOTRST Fuse is programmed and the Boot section size set to 8K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: ;Address Labels Code Comments .
8.2 Moving Interrupts Between Application and Boot Space The General Interrupt Control Register controls the placement of the Interrupt Vector table. 8.2.1 MCU Control Register – MCUCR Bit 7 6 5 4 3 2 1 0 JTD – – PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory.
AT90CAN32/64/128 • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below.
9. I/O-Ports 9.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
AT90CAN32/64/128 9.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 9-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 9-2. General Digital I/O(1) PUD D Q DDxn Q CLR WDx RESET 1 Q Pxn D 0 PORTxn Q CLR WPx DATA BUS RDx RESET WRx SLEEP RRx SYNCHRONIZER RPx D Q L Q D Q PINxn Q clk PUD: PULLUP DISABLE SLEEP: SLEEP CONTROL clk I/O Note: 9.2.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 9.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 9.2.
AT90CAN32/64/128 Figure 9-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 t 0xFF pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low.
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) ...
AT90CAN32/64/128 above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change. 9.2.6 9.3 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode).
Figure 9-5.
AT90CAN32/64/128 Generic Description of Overriding Signals for Alternate Functions Table 9-2. Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. PUOV Pull-up Override Value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.
• Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” for more details about this feature. 9.3.2 Alternate Functions of Port A The Port A has an alternate function as the address low byte and data lines for the External Memory Interface. The Port A pins with alternate functions are shown in Table 9-3. Table 9-3.
AT90CAN32/64/128 Table 9-4 and Table 9-5 relates the alternate functions of Port A to the overriding signals shown in Figure 9-5 on page 72. Table 9-4. Overriding Signals for Alternate Functions in PA7..
9.3.3 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 9-6. Table 9-6.
AT90CAN32/64/128 MOSI, SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB2 bit. • SCK – Port B, Bit 1 SCK, Master Clock output, Slave Clock input pin for SPI channel.
Overriding Signals for Alternate Functions in PB3..PB0 Table 9-8. 9.3.
AT90CAN32/64/128 • A14 – Port C, Bit 6 A14, External memory interface address 14. • A13 – Port C, Bit 5 A13, External memory interface address 13. • A12 – Port C, Bit 4 A12, External memory interface address 12. • A11 – Port C, Bit 3 A11, External memory interface address 11. • A10 – Port C, Bit 2 A10, External memory interface address 10. • A9 – Port C, Bit 1 A9, External memory interface address 9. • A8 – Port C, Bit 0 A8, External memory interface address 8.
Table 9-11. 9.3.5 Overriding Signals for Alternate Functions in PC3..
AT90CAN32/64/128 TXCAN, CAN Transmit Data (Data output pin for the CAN). When the CAN is enabled, this pin is configured as an output regardless of the value of DDD5. XCK1, USART1 External clock. The Data Direction Register (DDD5) controls whether the clock is output (DDD5 set) or input (DDD45 cleared). The XCK1 pin is active only when the USART1 operates in Synchronous mode. • ICP1 – Port D, Bit 4 ICP1, Input Capture Pin1. The PD4 pin can act as an input capture pin for Timer/Counter1.
Table 9-13 and Table 9-14 relates the alternate functions of Port D to the overriding signals shown in Figure 9-5 on page 72. Table 9-13.
AT90CAN32/64/128 9.3.6 Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 9-15. Table 9-15.
• AIN0/XCK0 – Port E, Bit 2 AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator. XCK0, USART0 External clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK0 pin is active only when the USART0 operates in Synchronous mode. • PDO/TXD0 – Port E, Bit 1 PDO, SPI Serial Programming Data Output.
AT90CAN32/64/128 Table 9-17. Signal Name PE3/AIN1/OC3A PE2/AIN0/XCK0 PE1/PDO/TXD0 PE0/PDI/RXD0 PUOE 0 0 TXEN0 RXEN0 PUOV 0 0 0 PORTE0 • PUD DDOE 0 0 TXEN0 RXEN0 DDOV 0 0 1 0 PVOE OC3A ENABLE UMSEL0 TXEN0 0 PVOV OC3A XCK0 OUTPUT TXD0 0 PTOE 0 0 0 0 (1) (1) DIEOE AIN1D AIN0D 0 0 DIEOV 0 0 0 0 DI 0 XCK0 INPUT – RXD0 AIO AIN1 INPUT AIN0 INPUT – – Note: 9.3.7 Overriding Signals for Alternate Functions in PE3..PE0 1.
TDI, JTAG Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin. • TCK, ADC6 – Port F, Bit 6 ADC6, Analog to Digital Converter, input channel 6. TDO, JTAG Test Data Out. Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin.
AT90CAN32/64/128 Table 9-19 and Table 9-20 relates the alternate functions of Port F to the overriding signals shown in Figure 9-5 on page 72. Table 9-19. Overriding Signals for Alternate Functions in PF7..
9.3.8 Alternate Functions of Port G The alternate pin configuration is as follows: Table 9-21. Port Pin Port G Pins Alternate Functions Alternate Function PG4 TOSC1 (RTC Oscillator Timer/Counter2) PG3 TOSC2 (RTC Oscillator Timer/Counter2) PG2 ALE (Address Latch Enable to external memory) PG1 RD (Read strobe to external memory) PG0 WR (Write strobe to external memory) The alternate pin configuration is as follows: • TOSC1 – Port G, Bit 4 TOSC2, Timer/Counter2 Oscillator pin 1.
AT90CAN32/64/128 Table 9-21 and Table 9-22 relates the alternate functions of Port G to the overriding signals shown in Figure 9-5 on page 72. Overriding Signals for Alternate Function in PG4 Table 9-22. Signal Name 9.4.1 - - PG4/TOSC1 PUOE AS2 PUOV 0 DDOE AS2 DDOV 0 PVOE 0 PVOV 0 PTOE 0 DIEOE AS2 DIEOV EXCLK DI – AIO T/C2 OSC INPUT Overriding Signals for Alternate Functions in PG3:0 Table 9-23. 9.
9.4.2 Port A Data Direction Register – DDRA Bit 9.4.3 7 6 5 4 3 2 1 0 DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Port A Input Pins Address – PINA Bit 9.4.
AT90CAN32/64/128 9.4.10 Port D Data Register – PORTD Bit 9.4.11 7 6 5 4 3 2 1 0 PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Port D Data Direction Register – DDRD Bit 9.4.
9.4.18 Port F Input Pins Address – PINF Bit 9.4.19 7 6 5 4 3 2 1 0 PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A 7 6 5 4 3 2 1 0 – – – PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Port G Data Register – PORTG Bit 9.4.
AT90CAN32/64/128 10. External Interrupts The External Interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the External Interrupt Control Registers – EICRA (INT3:0) and EICRB (INT7:4).
Asynchronous External Interrupt Sense Control(1) Table 10-1. ISCn1 ISCn0 0 0 The low level of INTn generates an interrupt request. 0 1 Any logical change on INTn generates an interrupt request 1 0 The falling edge of INTn generates asynchronously an interrupt request. 1 1 The rising edge of INTn generates asynchronously an interrupt request. Note: 1. n = 3, 2, 1 or 0.
AT90CAN32/64/128 10.0.3 External Interrupt Mask Register – EIMSK Bit 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 IINT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EIMSK • Bits 7..0 – INT7 – INT0: External Interrupt Request 7 - 0 Enable When an INT7 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled.
11. Timer/Counter3/1/0 Prescalers Timer/Counter3, Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter3, Timer/Counter1 and Timer/Counter0. 11.1 Overview Most bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number. 11.1.
AT90CAN32/64/128 Figure 11-1. T3/T1/T0 Pin Sampling D Tn Q D Q D Tn_sync (To Clock Select Logi Q LE clk I/O Synchronization Edge Detector The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T3/T1/T0 pin to the counter is updated.
11.2 11.2.1 Timer/Counter0/1/3 Prescalers Register Description General Timer/Counter Control Register – GTCCR Bit 7 6 5 4 3 2 1 0 TSM – – – – – PSR2 PSR310 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 GTCCR • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode.
AT90CAN32/64/128 12. 8-bit Timer/Counter0 with PWM Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: 12.1 Features • • • • • • • 12.
12.2.1 Registers The Timer/Counter (TCNT0) and Output Compare Register (OCR0A) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin.
AT90CAN32/64/128 Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0).
Figure 12-3 shows a block diagram of the Output Compare unit. Figure 12-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFn x (Int.Req. top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled.
AT90CAN32/64/128 generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is downcounting. The setup of the OC0A should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0A value is to use the Force Output Compare (FOC0A) strobe bits in Normal mode. The OC0A Register keeps its value even when changing between Waveform Generation modes.
12.6.2 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0A1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0A1:0 = 0 tells the Waveform Generator that no action on the OC0A Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 12-2 on page 110. For fast PWM mode, refer to Table 123 on page 110, and for phase correct PWM refer to Table 12-4 on page 111.
AT90CAN32/64/128 Figure 12-5. CTC Mode, Timing Diagram OCnx Interrupt Flag S TCNTn OCnx (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0A and TCNT0. Figure 12-6. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag OCRnx Update and TOVn Interrupt Flag S TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value.
AT90CAN32/64/128 12.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In noninverting Compare Output mode, the Output Compare (OC0A) is cleared on the compare match between TCNT0 and OCR0A while upcounting, and set on the compare match while downcounting.
decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = -----------------N ⋅ 510 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
AT90CAN32/64/128 Figure 12-10 shows the setting of OCF0A in all modes except CTC mode. Figure 12-10. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (fclk_I/O/8) clk I/O clk Tn (clk I/O /8) OCRnx - 1 TCNTn OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 12-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. Figure 12-11.
• Bit 6, 3 – WGM01:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 12-1 and “Modes of Operation” on page 104. Table 12-1.
AT90CAN32/64/128 Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 105 for more details. Table 12-4 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to phase correct PWM mode. Compare Output Mode, Phase Correct PWM Mode(1) Table 12-4. COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected.
12.9.3 Output Compare Register A – OCR0A Bit 7 6 5 4 3 2 1 0 OCR0A[7:0] OCR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0A pin. 12.9.
AT90CAN32/64/128 13. 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: 13.1 Features • • • • • • • • • • • 13.2 True 16-bit Design (i.e.
Figure 13-1. 16-bit Timer/Counter Block Diagram(1) TOVn Count (Int.Req.) Clear Control Logic clk Tn Direction Clock Select Tn Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn = = 0 OCFnA (Int.Req.) OCnA Waveform = Generation OCRnA OCFnB Fixed (Int.Req.) TOP Values DATABUS Generation OCRnB OCFnC (Int.Req.) Generation OCRnC ( From Analog ICFn ICRn TCCRnA 13.2.1 OCnC Waveform = Note: OCnB Waveform = TCCRnB Comparator Ouput ) (Int.Req.
AT90CAN32/64/128 uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkTn). The double buffered Output Compare Registers (OCRnx) are compared with the Timer/Counter value at all time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OCnx). See “Output Compare Units” on page 123..
The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. The following bits are added to the 16-bit Timer/Counter Control Registers: • COMnC1:0 are added to TCCRnA. • FOCnA, FOCnB and FOCnC are added to TCCRnC. • WGMn3 is added to TCCRnB. Interrupt flag and mask bits for output compare unit C are added. The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. 13.
AT90CAN32/64/128 13.3.1 Code Examples The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCRnx and ICRn Registers. Note that when using “C”, the compiler handles the 16-bit access. Assembly Code Examples(1) ... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF sts TCNTnH,r17 sts TCNTnL,r16 ; Read TCNTn into r17:r16 lds r16,TCNTnL lds r17,TCNTnH ...
The following code examples show how to do an atomic read of the TCNTn Register contents. Reading any of the OCRnx or ICRn Registers can be done by using the same principle.
AT90CAN32/64/128 The following code examples show how to do an atomic write of the TCNTn Register contents. Writing any of the OCRnx or ICRn Registers can be done by using the same principle.
13.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 13-2 shows a block diagram of the counter and its surroundings. Figure 13-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.
AT90CAN32/64/128 The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. 13.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICPn pin or alternatively, via the analog-comparator unit.
cleared when the interrupt is executed. Alternatively the ICFn flag can be cleared by software by writing a logical one to its I/O bit location. Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICRnH I/O location it will access the TEMP Register.
AT90CAN32/64/128 priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture.
Figure 13-4. Output Compare Unit, Block Diagram DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf.(8-bit)OCRnxL Buf.(8-bit) OCRnx TCNTnH (8-bit) Buffer (16-bit Register) OCRnxH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) OCRnxL (8-bit) OCRnx (16-bit Register) = (16-bit Comparator ) OCFnx TOP BOTTOM Waveform Generator WGMn3:0 (Int.Req.) OCnx COMnx1:0 The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes.
AT90CAN32/64/128 match had occurred (the COMnx1:0 bits settings define whether the OCnx pin is set, cleared or toggled). 13.7.2 Compare Match Blocking by TCNTn Write All CPU writes to the TCNTn Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCRnx to be initialized to the same value as TCNTn without triggering an interrupt when the Timer/Counter clock is enabled. 13.7.
Figure 13-5. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O 13.8.1 Compare Output Function The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
AT90CAN32/64/128 while the Waveform Generation mode bits do. The COMnx1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COMnx1:0 bits control whether the output should be set, cleared or toggle at a compare match (See “Compare Match Output Unit” on page 125.) For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 134. 13.9.1 Normal Mode The simplest mode of operation is the Normal mode (WGMn3:0 = 0).
An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature.
AT90CAN32/64/128 shows fast PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx interrupt flag will be set when a compare match occurs. Figure 13-7.
In fast PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COMnx1:0 to three (see Table on page 136). The actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OCnx).
AT90CAN32/64/128 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx interrupt flag will be set when a compare match occurs. Figure 13-8.
output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at the compare match between OCRnx and TCNTn when the counter increments, and clearing (or setting) the OCnx Register at compare match between OCRnx and TCNTn when the counter decrements.
AT90CAN32/64/128 Figure 13-9. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Se or ICFn Interrupt Flag (Interrupt on TOP) OCRnx/TOP Update and TOVn Interrupt Flag Se (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at BOTTOM).
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for noninverted PWM mode. For inverted PWM the output will have the opposite logic values. 13.
AT90CAN32/64/128 Figure 13-12. Timer/Counter Timing Diagram, no Prescaling clk I/O clk Tn (clk I/O/1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICF n (if used as TOP) OCRnx New OCRnx Value Old OCRnx Value (Update at TOP) Figure 13-13 shows the same timing data, but with the prescaler enabled. Figure 13-13.
• Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A • Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B • Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C The COMnA1:0, COMnB1:0 and COMnC1:0 control the Output Compare pins (OCnA, OCnB and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output overrides the normal port functionality of the I/O pin it is connected to.
AT90CAN32/64/128 Table 13-3 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Table 13-3. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1) COMnA1/COMnB1/ COMnC1 COMnA0/COMnB0/ COMnC0 0 0 Normal port operation, OCnA/OCnB/OCnC disconnected. 1 WGMn3=0: Normal port operation, OCnA/OCnB/OCnC disconnected. WGMn3=1: Toggle OCnA on Compare Match, OCnB/OCnC reserved.
Waveform Generation Mode Bit Description (1) Table 13-4.
AT90CAN32/64/128 This bit selects which edge on the Input Capture pin (ICPn) that is used to trigger a capture event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and when the ICESn bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICESn setting, the counter value is copied into the Input Capture Register (ICRn).
13.11.6 Timer/Counter3 Control Register C – TCCR3C Bit 7 6 5 4 3 2 1 FOC3A FOC3B FOC3C – – – – 0 – Read/Write R/W R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0 TCCR3C • Bit 7 – FOCnA: Force Output Compare for Channel A • Bit 6 – FOCnB: Force Output Compare for Channel B • Bit 5 – FOCnC: Force Output Compare for Channel C The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM mode.
AT90CAN32/64/128 13.11.9 Output Compare Register A – OCR1AH and OCR1AL Bit 7 6 5 4 3 2 1 0 OCR1A[15:8] OCR1AH OCR1A[7:0] OCR1AL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 4 3 2 1 0 13.11.10 Output Compare Register B – OCR1BH and OCR1BL Bit 7 6 5 OCR1B[15:8] OCR1BH OCR1B[7:0] OCR1BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 4 3 2 1 0 13.11.
13.11.15 Input Capture Register – ICR1H and ICR1L Bit 7 6 5 4 3 2 1 0 ICR1[15:8] ICR1H ICR1[7:0] ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 5 4 3 2 1 0 13.11.
AT90CAN32/64/128 • Bit 2 – OCIEnB: Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 60.) is executed when the OCFnB flag, located in TIFRn, is set.
• Bit 2 – OCFnB: Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output Compare Register B (OCRnB). Note that a Forced Output Compare (FOCnB) strobe will not set the OCFnB flag. OCFnB is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCFnB can be cleared by writing a logic one to its bit location.
AT90CAN32/64/128 14. 8-bit Timer/Counter2 with PWM and Asynchronous Operation Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: 14.1 Features • • • • • • • 14.
Figure 14-1. 8-bit Timer/Counter2 Block Diagram TCCRnx count TOVn (Int.Req.) clear Control Logic clk Tn direction TOSC2 BOTTOM TOP Prescaler T/C Oscillator TOSC1 Timer/Counter TCNTn = 0 = 0xFF DATA BUS OCnx (Int.Req.) Waveform Generation = clkI/O OCnx OCRnx clkI/O Synchronized Status flags Synchronization Unit clkASY Status flags ASSRn asynchronous mode select (ASn) The Timer/Counter (TCNT2) and Output Compare Register (OCR2A) are 8-bit registers. Interrupt request (shorten as Int.Req.
AT90CAN32/64/128 14.2.1 Definitions The following definitions are used extensively throughout the section: 14.3 BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00). MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2A Register.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of whether clkT2 is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
AT90CAN32/64/128 Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR2A Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR2A Buffer Register, and if double buffering is disabled the CPU will access the OCR2A directly. 14.5.
Figure 14-5. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O 14.6.1 Compare Output Function The general I/O port function is overridden by the Output Compare (OC2A) from the Waveform Generator if either of the COM2A1:0 bits are set. However, the OC2A pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
AT90CAN32/64/128 For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 154. 14.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00).
For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC2A = fclk_I/O/2 when OCR2A is set to zero (0x00).
AT90CAN32/64/128 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin. Setting the COM2A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM2A1:0 to three (See Table 14-3 on page 157).
Figure 14-8. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag S OCRnx Update TOVn Interrupt Flag S TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin.
AT90CAN32/64/128 Figure 14-9. Timer/Counter Timing Diagram, no Prescaling clk I/O clk Tn (clk I/O /1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 14-10 shows the same timing data, but with the prescaler enabled. Figure 14-10. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clk I/O clk Tn (clk I/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 14-11 shows the setting of OCF2A in all modes except CTC mode. Figure 14-11.
Figure 14-12 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 14-12. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) clk I/O clk Tn (clk I/O /8) TCNTn TOP - 1 (CTC) TOP OCRnx BOTTOM BOTTOM + 1 TOP OCFnx 14.9 8-bit Timer/Counter Register Description 14.9.
AT90CAN32/64/128 two types of Pulse Width Modulation (PWM) modes. See Table 14-1 and “Modes of Operation” on page 150. Table 14-1. Waveform Generation Mode Bit Description(1) Mode WGM21 (CTC2) WGM20 (PWM2) Timer/Counter Mode of Operation TOP Update of OCR2A at TOV2 Flag Set on 0 0 0 Normal 0xFF Immediate MAX 1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 1 0 CTC OCR2A Immediate MAX 3 1 1 Fast PWM 0xFF TOP MAX Note: 1. The CTC2 and PWM2 bit definition names are now obsolete.
Table 14-4 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct PWM mode. Table 14-4. Compare Output Mode, Phase Correct PWM Mode(1) COM2A1 COM2A0 0 0 Normal port operation, OC2A disconnected. 0 1 Reserved 1 0 Clear OC2A on compare match when up-counting. Set OC2A on compare match when downcounting. 1 1 Set OC2A on compare match when up-counting. Clear OC2A on compare match when downcounting. Note: Description 1.
AT90CAN32/64/128 The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2A pin. 14.10 Asynchronous operation of the Timer/Counter2 14.10.1 Asynchronous Status Register – ASSR Bit 7 6 5 4 3 2 1 0 – – – EXCLK AS2 TCN2UB OCR2UB TCR2UB Read/Write R R R R/W R/W R R R Initial Value 0 0 0 0 0 0 0 0 ASSR • Bit 7..
14.10.2 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the timer registers TCNT2, OCR2A, and TCCR2A might be corrupted. A safe procedure for switching clock source is: a. Disable the Timer/Counter2 interrupts by clearing OCIE2A and TOIE2. b. Select clock source by setting AS2 and EXCLK as appropriate. c.
AT90CAN32/64/128 • Description of wake up from Power-save mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP.
• Bit 7..2 – Reserved Bits These bits are reserved for future use. • Bit 1 – OCF2A: Output Compare Flag 2 A The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic one to the flag.
AT90CAN32/64/128 Figure 14-14. Timer/Counter2 Crystal Oscillator Connections 12 - 22 pF TOSC2 32.768 KHz TOSC1 12 - 22 pF GND A external clock can also be used using TOSC1 as input. Setting AS2 and EXCLK enables this configuration. Figure 14-15. Timer/Counter2 External Clock Connections NC TOSC2 External Clock Signal TOSC1 For Timer/Counter2, the possible prescaled selections are: clk T2S /8, clk T2S/32, clk T2S /64, clkT2S/128, clkT2S/256, and clkT2S/1024.
15. Output Compare Modulator - OCM 15.1 Overview Many register and bit references in this section are written in general form. • A lower case “n” replaces the Timer/Counter number, in this case 0 and 1. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on. • A lower case “x” replaces the Output Compare unit channel, in this case A or C.
AT90CAN32/64/128 Figure 15-2. Output Compare Modulator, Schematic COM0A1 Vcc COM0A0 COM1C1 Modulator COM1C0 (From T/C1 0 D 1 Q Waveform Generator) 1 OC1C Pin 0 (From T/C0 D OC0A / OC1C / PB7 Q Waveform Generator) OC0A D Q D PORTB7 Q DDRB7 DATABUS 15.2.1 Timing Example Figure 15-3 illustrates the modulator in action.
15.2.2 166 Resolution of the PWM Signal The resolution of the PWM signal (OC1C) is reduced by the modulation. The reduction factor is equal to the number of system clock cycles of one period of the carrier (OC0A). In this example the resolution is reduced by a factor of two. The reason for the reduction is illustrated in Figure 15-3 at the second and third period of the PB7 output when PORTB7 equals zero.
AT90CAN32/64/128 16. Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90CAN32/64/128 and peripheral devices or between several AVR devices. The AT90CAN32/64/128 SPI includes the following features: 16.
The interconnection between Master and Slave CPUs with SPI is shown in Figure 16-2. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data.
AT90CAN32/64/128 When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 16-1. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 71. Table 16-1. Pin SPI Pin Overrides(1) Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1.
DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB2, replace DD_MOSI with DDB2 and DDR_SPI with DDRB.
AT90CAN32/64/128 The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high. The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master clock generator. When the SS pin is driven high, the SPI slave will immediately reset the send and receive logic, and drop any partially received data in the Shift Register. 16.2.
AT90CAN32/64/128 and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to Figure 16-3 and Figure 16-4 for an example. The CPOL functionality is summarized below: CPOL Functionality Table 16-2.
16.2.4 SPI Status Register – SPSR Bit 7 6 5 4 3 2 1 0 SPIF WCOL – – – – – SPI2X Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 SPSR • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF flag.
AT90CAN32/64/128 nal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 16-2 and Table 16-3, as done below: Table 16-5. CPOL Functionality Leading Edge Trailing Edge SPI Mode CPOL=0, CPHA=0 Sample (Rising) Setup (Falling) 0 CPOL=0, CPHA=1 Setup (Rising) Sample (Falling) 1 CPOL=1, CPHA=0 Sample (Falling) Setup (Rising) 2 CPOL=1, CPHA=1 Setup (Falling) Sample (Rising) 3 Figure 16-3.
17. USART (USART0 and USART1) The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: 17.1 Features • • • • • • • • • • • • 17.
AT90CAN32/64/128 Figure 17-1. USARTn Block Diagram (1) Clock Generator UBRRn[H:L] CLKio BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCKn Transmitter TX UDRn (Transmit) CONTROL DATA BUS PARITY GENERATOR CONTROL TxDn Receiver RECEIVE SHIFT REGISTER UDRn (Receive) UCSRAn Note: PIN TRANSMIT SHIFT REGISTER CLOCK RX RECOVERY CONTROL DATA PIN RECOVERY CONTROL RxDn PARITY CHECKER UCSRBn UCSRCn 1.
17.4 Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USARTn supports four modes of clock operation: Normal asynchronous, Double Speed asynchronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USARTn Control and Status Register C (UCSRnC) selects between asynchronous and synchronous operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the UCSRnA Register.
AT90CAN32/64/128 units use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the UMSELn, U2Xn and DDR_XCKn bits. Table 17-1 contains equations for calculating the baud rate (in bits per second) and for calculating the UBRRn value for each mode of operation using an internally generated clock source. Table 17-1.
Note that fclkio depends on the stability of the system clock source. It is therefore recommended to add some margin to avoid possible loss of data due to frequency variations. 17.4.4 Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same.
AT90CAN32/64/128 Figure 17-4. Frame Formats FRAME (IDLE) St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] St Start bit, always low. (n) Data bits (0 to 8). P Parity bit. Can be odd or even. Sp Stop bit, always high. IDLE No transfers on the communication line (RxDn or TxDn). An IDLE line must be high. (St / IDLE) The frame format used by the USARTn is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting.
check that there are no unread data in the receive buffer. Note that the TXCn flag must be cleared before each transmission (before UDRn is written) if it is used for this purpose. The following simple USART0 initialization code examples show one assembly and one C function that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter.
AT90CAN32/64/128 chronous operation is used, the clock on the XCKn pin will be overridden and used as transmission clock. 17.7.1 Sending Frames with 5 to 8 Data Bit A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing to the UDRn I/O location. The buffered data in the transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new frame.
17.7.2 Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8n bit in UCSRnB before the low byte of the character is written to UDRn. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16.
AT90CAN32/64/128 The Data Register Empty (UDREn) flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the Shift Register. For compatibility with future devices, always write this bit to zero when writing the UCSRnA Register.
The following code example shows a simple USART0 receive function based on polling of the Receive Complete (RXC0) flag. When using frames with less than eight bits the most significant bits of the data read from the UDR0 will be masked to zero. The USART0 has to be initialized before the function can be used.
AT90CAN32/64/128 The following code example shows a simple USART0 receive function that handles both nine bit characters and the status bits.
17.8.3 Receive Complete Flag and Interrupt The USARTn Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero.
AT90CAN32/64/128 The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. 17.8.6 Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e.
izontal arrows illustrate the synchronization variation due to the sampling process. Note the larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxDn line is idle (i.e., no communication activity). Figure 17-5.
AT90CAN32/64/128 Figure 17-7 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. Figure 17-7. Stop Bit Sampling and Next Start Bit Sampling RxDn STOP 1 (A) (B) (C) Sample (U2Xn = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample (U2Xn = 1) 1 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame.
Table 17-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0) D # (Data + Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 93.20 106.67 +6.67/-6.8 ± 3.0 6 94.12 105.79 +5.79/-5.88 ± 2.5 7 94.81 105.11 +5.11/-5.19 ± 2.0 8 95.36 104.58 +4.58/-4.54 ± 2.0 9 95.81 104.14 +4.14/-4.19 ± 1.5 10 96.17 103.78 +3.78/-3.83 ± 1.5 Table 17-3.
AT90CAN32/64/128 17.10.1 MPCM Protocol If the Receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indicates if the frame contains data or address information. If the Receiver is set up for frames with nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame.
17.11 USART Register Description 17.11.1 USART0 I/O Data Register – UDR0 Bit 17.11.
AT90CAN32/64/128 • Bit 6 – TXCn: USARTn Transmit Complete This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer (UDRn). The TXCn flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXCn flag can generate a Transmit Complete interrupt (see description of the TXCIEn bit).
17.11.6 USART1 Control and Status Register B – UCSR1B Bit 7 6 5 4 3 2 1 0 RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0 UCSR1B • Bit 7 – RXCIEn: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXCn flag.
AT90CAN32/64/128 17.11.8 USART1 Control and Status Register C – UCSR1C Bit 7 6 5 4 3 2 1 0 – UMSEL1 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPO1L Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 1 1 0 UCSR1C • Bit 7 – Reserved Bit This bit is reserved for future use. For compatibility with future devices, these bit must be written to zero when UCSRnC is written.
• Bit 2:1 – UCSZn1:0: Character Size The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits (Character SiZe) in a frame the Receiver and Transmitter use. Table 17-7. UCSZn Bits Settings UCSZn2 UCSZn1 UCSZn0 Character Size 0 0 0 5-bit 0 0 1 6-bit 0 1 0 7-bit 0 1 1 8-bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9-bit • Bit 0 – UCPOLn: Clock Polarity This bit is used for synchronous mode only.
AT90CAN32/64/128 • Bit 15:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRnH is written. • Bit 11:0 – UBRRn11:0: USARTn Baud Rate Register This is a 12-bit register which contains the USARTn baud rate. The UBRRnH contains the four most significant bits, and the UBRRnL contains the eight least significant bits of the USARTn baud rate.
Table 17-10. Examples of UBRRn Settings for Commonly Frequencies (Continued) fclkio = 3.6864 MHz fclkio = 4.0000 MHz fclkio = 7.3728 MHz Baud Rate (bps) U2Xn = 0 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0% 28.
AT90CAN32/64/128 Table 17-11. Examples of UBRRn Settings for Commonly Frequencies (Continued) Baud Rate (bps) fclkio = 8.0000 MHz U2Xn = 0 UBRRn Error fclkio = 10.000 MHz U2Xn = 1 UBRRn Error U2Xn = 0 UBRRn Error fclkio = 11.0592 MHz U2Xn = 1 UBRRn Error U2Xn = 0 UBRRn Error U2Xn = 1 UBRRn Error 2400 207 0.2% 416 -0.1% 259 0.2% 520 0.0% 287 0.0% 575 0.0% 4800 103 0.2% 207 0.2% 129 0.2% 259 0.2% 143 0.0% 287 0.0% 9600 51 0.2% 103 0.2% 64 0.2% 129 0.2% 71 0.
Table 17-12. Examples of UBRRn Settings for Commonly Frequencies (Continued) Baud Rate (bps) fclkio = 12.0000 MHz U2Xn = 0 UBRRn Error fclkio = 14.7456 MHz U2Xn = 1 UBRRn Error U2Xn = 0 UBRRn Error fclkio = 16.0000 MHz U2Xn = 1 UBRRn Error U2Xn = 0 UBRRn Error U2Xn = 1 UBRRn Error 2400 312 -0.2% 624 0.0% 383 0.0% 767 0.0% 416 -0.1% 832 0.0% 4800 155 0.2% 312 -0.2% 191 0.0% 383 0.0% 207 0.2% 416 -0.1% 9600 77 0.2% 155 0.2% 95 0.0% 191 0.0% 103 0.2% 207 0.
AT90CAN32/64/128 18. Two-wire Serial Interface 18.1 Features • • • • • • • • • • 18.
18.2.2 Electrical Interconnection As depicted in Figure 18-1, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the operation of the interface. A low level on a TWI bus line is generated when one or more TWI devices output a zero.
AT90CAN32/64/128 Figure 18-3. START, REPEATED START and STOP Conditions SDA SCL STOP START START 18.3.3 REPEATED START STOP Address Packet Format All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is to be performed, otherwise a write operation should be performed.
Acknowledge (ACK) is signalled by the receiver pulling the SDA line low during the ninth SCL cycle. If the receiver leaves the SDA line high, a NACK is signalled. When the receiver has received the last byte, or for some reason cannot receive any more bytes, it should inform the transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first. Figure 18-5.
AT90CAN32/64/128 • An algorithm must be implemented allowing only one of the masters to complete the transmission. All other masters should cease transmission when they discover that they have lost the selection process. This selection process is called arbitration. When a contending master discovers that it has lost the arbitration process, it should immediately switch to slave mode to check whether it is being addressed by the winning master.
Figure 18-8. Arbitration Between two Masters START SDA from Master A Master A loses Arbitration,A SDA SDA SDA from Master B SDA Line Synchronized SCL Line Note that arbitration is not allowed between: • A REPEATED START condition and a data bit • A STOP condition and a data bit • A REPEATED START and a STOP condition It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur.
AT90CAN32/64/128 Figure 18-9. Overview of the TWI Module SCL SDA Slew-rate Spike Filter Control Slew-rate Spike Filter Control Bus Interface Unit START / STOP Control Bit Rate Generator Spike Suppression Arbitration detection Prescaler Address/Data Shift Ack Register (TWDR) Address Match Unit Address Register (TWAR) Address Comparator Bit Rate Register (TWBR) Control Unit Status Register (TWSR) Control Register (TWCR) State Machine and Status control TWI Unit 18.5.
18.5.3 Bus Interface Unit This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted, or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK Register is not directly accessible by the application software.
AT90CAN32/64/128 • When a bus error has occurred due to an illegal START or STOP condition 18.6 18.6.1 TWI Register Description TWI Bit Rate Register – TWBR Bit 7 6 5 4 3 2 1 0 TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TWBR • Bits 7.0 – TWI Bit Rate Register TWBR selects the division factor for the bit rate generator.
The application writes the TWSTA bit to one when it desires to become a master on the Twowire Serial Bus. The TWI hardware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master status. TWSTA must be cleared by software when the START condition has been transmitted.
AT90CAN32/64/128 • Bits 1.0 – TWPS: TWI Prescaler Bits These bits can be read and written, and control the bit rate prescaler. TWI Bit Rate Prescaler Table 18-2. TWPS1 TWPS0 Prescaler Value 0 0 1 0 1 4 1 0 16 1 1 64 To calculate bit rates, see “Bit Rate Generator Unit” on page 209. The value of TWPS1.0 is used in the equation. 18.6.
TWGCE is used to enable recognition of the general call address (0x00). There is an associated address comparator that looks for the slave address (or general call address if enabled) in the received serial address. If a match is found, an interrupt request is generated. If set, this bit enables the recognition of a General Call given over the TWI Serial Bus. 18.7 Using the TWI The AVR TWI is byte-oriented and interrupt based.
AT90CAN32/64/128 the application has cleared TWINT, the TWI will initiate transmission of the START condition. 2. When the START condition has been transmitted, the TWINT flag in TWCR is set, and TWSR is updated with a status code indicating that the START condition has successfully been sent. 3. The application software should now examine the value of TWSR, to make sure that the START condition was successfully transmitted.
• When the TWINT flag is set, the user must update all TWI Registers with the value relevant for the next TWI bus cycle. As an example, TWDR must be loaded with the value to be transmitted in the next bus cycle. • After all TWI Register updates and other pending application software tasks have been completed, TWCR is written. When writing TWCR, the TWINT bit should be set. Writing a one to TWINT clears the flag. The TWI will then commence executing whatever operation was specified by the TWCR setting.
AT90CAN32/64/128 18.8 Transmission Modes The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters are present in the system, some of these might transmit data to the TWI, and then SR mode would be used.
Figure 18-11. Data Transfer in Master Transmitter Mode Device 1 Device 2 Device 3 MASTER SLAVE TRANSMITTER RECEIVER ........ Device n V R1 CC R2 SDA SCL A START condition is sent by writing the following value to TWCR: TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 1 X 1 0 X 1 0 X TWEN must be set to enable the Two-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be written to one to clear the TWINT flag.
AT90CAN32/64/128 After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same slave again, or a new slave without transmitting a STOP condition. Repeated START enables the master to switch between slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus. Table 18-3.
Figure 18-12.
AT90CAN32/64/128 18.8.2 Master Receiver Mode In the Master Receiver Mode, a number of data bytes are received from a slave transmitter (see Figure 18-13). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered.
A REPEATED START condition is generated by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 1 X 1 0 X 1 0 X value After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same slave again, or a new slave without transmitting a STOP condition. Repeated START enables the master to switch between slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus. Figure 18-14.
AT90CAN32/64/128 Table 18-4.
To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 value TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE Device’s Own Slave Address The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address.
AT90CAN32/64/128 Table 18-5.
Figure 18-16. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes.
AT90CAN32/64/128 18.8.4 Slave Transmitter Mode In the Slave Transmitter mode, a number of data bytes are transmitted to a master receiver (see Figure 18-17). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 18-17. Data Transfer in Slave Transmitter Mode Device 1 Device 2 SLAVE TRANSMITTER MASTER RECEIVER Device 3 ........
While TWEA is zero, the TWI does not respond to its own slave address. However, the Two-wire Serial Bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the TWI from the Two-wire Serial Bus. In all sleep modes other than Idle mode, the clock system to the TWI is turned off.
AT90CAN32/64/128 Figure 18-18. Formats and States in the Slave Transmitter Mode Reception of the own slave address and one or more data bytes S SLA R A DATA A 0xA8 Arbitration lost as master and addressed as slave DATA 0xB8 A P or S 0xC0 A 0xB0 Last data byte transmitted. Switched to not addressed slave (TWEA = '0') A All 1's P or S 0xC8 From master to slave DATA From slave to master 18.8.
18.8.6 Combining Several TWI Modes In some cases, several TWI modes must be combined in order to complete the desired action. Consider for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps: 1. The transfer must be initiated 2. The EEPROM must be instructed what location should be read 3. The reading must be performed 4. The transfer must be finished Note that data is transmitted both from master to slave and vice versa.
AT90CAN32/64/128 18.9 Multi-master Systems and Arbitration If multiple masters are connected to the same bus, transmissions may be initiated simultaneously by one or more of them. The TWI standard ensures that such situations are handled in such a way that one of the masters will be allowed to proceed with the transfer, and that no data will be lost in the process. An example of an arbitration situation is depicted below, where two masters are trying to transmit data to a slave receiver. Figure 18-20.
This is summarized in Figure 18-21. Possible status values are given in circles. Figure 18-21.
AT90CAN32/64/128 19. Controller Area Network - CAN The Controller Area Network (CAN) protocol is a real-time, serial, broadcast protocol with a very high level of security. The AT90CAN32/64/128 CAN controller is fully compatible with the CAN Specification 2.0 Part A and Part B.
by which the dominant state overwrites the recessive state. The competition for bus allocation is lost by all nodes with recessive transmission and dominant observation. All the "losers" automatically become receivers of the message with the highest priority and do not re-attempt transmission until the bus is available again. 19.2.2 19.2.2.1 Message Formats The CAN protocol supports two message frame formats, the only essential difference being in the length of the identifier.
AT90CAN32/64/128 19.2.2.2 CAN Extended Frame Figure 19-2. CAN Extended Frames Data Frame Bus Idle 11-bit base identifier SRR IDE IDT28..18 SOF Interframe Space 18-bit identifier extension RTR r1 ID17..0 Arbitration Field r0 4-bit DLC DLC4..0 0 - 8 bytes Control Field 15-bit CRC CRC ACK ACK del. del. Data Field CRC Field ACK Field 7 bits IntermissionBus Idle 3 bits (Indefini End of Frame Interframe Space Remote Frame Bus Idle 11-bit base identifier SRR IDE IDT28..
Figure 19-3. CAN Bit Construction CAN Frame (producer) Transmission Point (producer) Nominal CAN Bit Time Time Quantum (producer) Segments (producer) SYNC_SEG PROP_SEG PHASE_SEG_1 PHASE_SEG_2 propagation delay Segments (consumer) SYNC_SEG PROP_SEG PHASE_SEG_1 PHASE_SEG_2 Sample Point 19.2.3.2 Synchronization Segment The first segment is used to synchronize the various bus nodes. On transmission, at the start of this segment, the current bit level is output.
AT90CAN32/64/128 The IPT begins at the sample point, is measured in TQ and is fixed at 2TQ for the Atmel CAN. Since Phase Segment 2 also begins at the sample point and is the last segment in the bit time, PS2 minimum shall not be less than the IPT. 19.2.3.8 Bit Lengthening As a result of resynchronization, Phase Segment 1 may be lengthened or Phase Segment 2 may be shortened to compensate for oscillator tolerances.
Figure 19-4. Bus Arbitration Arbitration lost node A TXCAN Node A loses the bu Node B wins the bus node B TXCAN CAN bus SOF ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR IDE 19.2.5 - - - - - Errors The CAN protocol signals any errors immediately as they occur. Three error detection mechanisms are implemented at the message level and two at the bit level: 19.2.5.
AT90CAN32/64/128 19.3 CAN Controller The CAN controller implemented into AT90CAN32/64/128 offers V2.0B Active. This full-CAN controller provides the whole hardware for convenient acceptance filtering and message management. For each message to be transmitted or received this module contains one so called message object in which all information regarding the message (e.g. identifier, data bytes etc.) are stored.
19.4 19.4.1 CAN Channel Configuration The CAN channel can be in: • Enabled mode In this mode: – the CAN channel (internal TxCAN & RxCAN) is enabled, – the input clock is enabled. • Standby mode In standby mode: – the transmitter constantly provides a recessive level (on internal TxCAN) and the receiver is disabled, – input clock is enabled, – the registers and pages remain accessible.
AT90CAN32/64/128 The total number of TQ in a bit time has to be programmed at least from 8 to 25. Figure 19-7. Sample and Transmission Point Bit Timing PRS (3-bit length) PHS1 (3-bit length) CLK Prescaler BRP IO Sample Point Fcan (Tscl) Time Quantum PHS2 (3-bit length) Transmission Point SJW (2-bit length) Figure 19-8. General Structure of a Bit Period 1 CLK /CLK IO IO Bit Rate Prescaler Tscl (TQ) F CAN one nominal bit Data Tsyns(5) Notes: 2. 3. 4. 5. 1.
5. Tsjw = (1 to 4) x Tscl = (SJW[1..0]+ 1) x Tscl Notes: 1. The total number of Tscl (Time Quanta) in a bit time must be between 8 to 25. 2. PHS2[2..0] 2 is programmable to be ≤ PHS1[2..0] and ≥ 1. 19.4.4 Fault Confinement (c.f. Section 19.7 ”Error Management” on page 246). 19.4.5 Overload Frame An overload frame is sent by setting an overload request (OVRQ). After the next reception, the CAN channel sends an overload frame in accordance with the CAN specification.
AT90CAN32/64/128 Table 19-1. MOb Configuration (Continued) MOb Configuration 1 Reply Valid RTR Tag x 0 0 0 1 1 19.5.1.1 1 x 1 x Operating Mode Rx Data Frame Rx Remote Frame Rx Remote Frame then, Tx Data Frame (reply) Frame Buffer Receive Mode Disabled In this mode, the MOb is “free”. 19.5.1.2 Tx Data & Remote Frame 1.
6. All the parameters and data are available in the MOb until a new initialization. 19.5.1.4 Automatic Reply A reply (data frame) to a remote frame can be automatically sent after reception of the expected remote frame. 1. Several fields must be initialized before receiving the remote frame: – (c.f. Section 19.5.1.3 ”Rx Data & Remote Frame” on page 243) 2. When a remote frame matches, automatically the RTRTAG and the reply valid bit (RPLV) are reset. No flag (or interrupt) is set at this time.
AT90CAN32/64/128 Figure 19-10. Acceptance Filter Block Diagram internal RxDcan Rx Shift Register (internal) ID &RB RTR IDE 13(32) = Hit MOb[ 13(32) Write Enable 13(32) ID &RB 1 13(32) RTRTAG IDE 13(32) IDMSK CANIDT Registers & CANCDMOB (MOb[i]) Note: RTRMSK IDEMSK CANIDM Registers (MOb[i]) Examples: Full filtering: to accept only ID = 0x317 in part A. - ID MSK = 111 1111 1111 b - ID TAG = 011 0001 0111 b Partiel filtering: to accept ID from 0x310 up to 0x317 in part A.
19.6 CAN Timer A programmable 16-bit timer is used for message stamping and time trigger communication (TTC). Figure 19-11. CAN Timer Block Diagram clk 8 IO ENFG CANTCON clkCANTIM TTC OVRTIM overrun TXOK[i] "EOF " "SOF " RXOK[i] CANSTM[i] 19.6.1 SYNCTTC CANTIM CANTTC Prescaler An 8-bit prescaler is initialized by CANTCON register. It receives the clkIO frequency divided by 8. It provides clkCANTIM frequency to the CAN Timer if the CAN controller is enabled.
AT90CAN32/64/128 • Error active (default): The CAN channel takes part in bus communication and can send an active error frame when the CAN macro detects an error. • Error passive: The CAN channel cannot send an active error frame. It takes part in bus communication, but when an error is detected, a passive error frame is sent. Also, after a transmission, an error passive unit will wait before initiating further transmission. • Bus off: The CAN channel is not allowed to have any influence on the bus.
• AERR: Acknowledgment error (Tx only). No detection of the dominant bit in the acknowledge slot. Figure 19-13. Error Detection Procedures in a Data Frame Arbitration Bit error Stuff error Form error Tx ACK error SOF Rx Identifier RTR Command Message Data CRC CRC ACK ACK del. del. EOF inter. Bit error Stuff error Form error CRC error 19.7.3 Error Setting The CAN channel can detect some errors on the CAN network. • In transmission: The error is set at MOb level.
AT90CAN32/64/128 Figure 19-14. CAN Controller Interrupt Structure CANGIE.4 CANGIE.5 ENTX ENRX CANGIE.3 ENERR CANSIT 1/2 SIT[i] CANSTMOB.6 TXOK[i] CANSTMOB.5 RXOK[i] CANSTMOB.4 BERR[i] CANSTMOB.3 SERR[i] CANSTMOB.2 CERR[i] CANSTMOB.1 FERR[i] CANSTMOB.0 AERR[i] CANIE 1/2 IEMOB[i] i=0 CANGIT.7 i=14 CANGIE.2 ENBX CANGIT.4 BXOK CANGIT.3 SERG CANGIT.2 CERG CANGIT.1 FERG CANGIT.0 AERG CANGIT.6 BOFFI CANGIT.5 OVRTIM CANGIE.1 ENERG CANGIE.6 ENBOFF CANIT CANGIE.
19.9 CAN Register Description Figure 19-15.
AT90CAN32/64/128 19.10 General CAN Registers 19.10.1 CAN General Control Register - CANGCON Bit 7 6 5 4 3 2 1 0 ABRQ OVRQ TTC SYNTTC LISTEN TEST ENA/STB SWRES Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 CANGCON • Bit 7 – ABRQ: Abort Request This is not an auto resettable bit. – 0 - no request. – 1 - abort request: a reset of CANEN1 and CANEN2 registers is done.
– 0 - standby mode: the on-going communication is normally terminated and the CAN channel is frozen (the CONMOB bits of every MOb do not change). The transmitter constantly provides a recessive level. In this mode, the receiver is not enabled but all the registers and mailbox remain accessible from CPU. – 1 - enable mode: the CAN channel enters in enable mode once 11 recessive bits has been read. • Bit 0 – SWRES: Software Reset Request This auto resettable bit only resets the CAN controller.
AT90CAN32/64/128 • Bit 1 – BOFF: Bus Off Mode BOFF gives the information of the state of the CAN channel. Only entering in bus off mode generates the BOFFIT interrupt. – 0 - no bus off mode. – 1 - bus off mode. • Bit 0 – ERRP: Error Passive Mode ERRP gives the information of the state of the CAN channel. This flag does not generate an interrupt. – 0 - no error passive mode. – 1 - error passive mode. 19.10.
– 1 - stuff error interrupt: detection of more than 5 consecutive bits with the same polarity. • Bit 2 – CERG: CRC Error General Writing a logical one resets this interrupt flag. – 0 - no interrupt. – 1 - CRC error interrupt: the CRC check on destuffed message does not fit with the CRC field. • Bit 1 – FERG: Form Error General Writing a logical one resets this interrupt flag. – 0 - no interrupt.
AT90CAN32/64/128 • Bit 2 – ENBX: Enable Frame Buffer Interrupt – 0 - interrupt disabled. – 1- frame buffer interrupt enabled. • Bit 1 – ENERG: Enable General Errors Interrupt – 0 - interrupt disabled. – 1- general errors interrupt enabled. • Bit 0 – ENOVRT: Enable CAN Timer Overrun Interrupt – 0 - interrupt disabled. – 1- CAN timer interrupt overrun enabled. 19.10.
• Bits 14:0 - IEMOB14:0: Interrupt Enable by MOb – 0 - interrupt disabled. – 1 - MOb interrupt enabled Note: Example: CANIE2 = 0000 1100b : enable of interrupts on MOb 2 & 3. • Bit 15 – Reserved Bit This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANIE1 is written. 19.10.
AT90CAN32/64/128 19.10.9 CAN Bit Timing Register 2 - CANBT2 Bit 7 6 5 4 3 2 1 - SJW1 SJW0 - PRS2 PRS1 PRS0 0 - Read/Write - R/W R/W - R/W R/W R/W - Initial Value - 0 0 - 0 0 0 - CANBT2 • Bit 7– Reserved Bit This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT2 is written.
• Bit 3:1 – PHS12:0: Phase Segment 1 This phase is used to compensate for phase edge errors. This segment may be lengthened by the re-synchronization jump width. Tphs1 = Tscl x (PHS1 [2:0] + 1) • Bit 0 – SMP: Sample Point(s) – 0 - once, at the sample point. – 1 - three times, the threefold sampling of the bus is the sample point and twice over a distance of a 1/2 period of the Tscl. The result corresponds to the majority decision of the three values. 19.10.
AT90CAN32/64/128 19.10.14 CAN Transmit Error Counter Register - CANTEC Bit 7 6 5 4 3 2 1 0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 CANTEC • Bit 7:0 – TEC7:0: Transmit Error Count CAN transmit error counter range 0 to 255. 19.10.
19.11 MOb Registers The MOb registers has no initial (default) value after RESET. 19.11.1 CAN MOb Status Register - CANSTMOB Bit 7 6 5 4 3 2 1 0 DLCW TXOK RXOK BERR SERR CERR FERR AERR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value - - - - - - - - CANSTMOB • Bit 7 – DLCW: Data Length Code Warning The incoming message does not have the DLC expected. Whatever the frame type, the DLC field of the CANCDMOB register is updated by the received DLC.
AT90CAN32/64/128 • Bit 1 – FERR: Form Error This flag can generate an interrupt. It must be cleared using a read-modify-write software routine on the whole CANSTMOB register. The form error results from one or more violations of the fixed form in the following bit fields: • CRC delimiter. • Acknowledgment delimiter. • EOF • Bit 0 – AERR: Acknowledgment Error This flag can generate an interrupt. It must be cleared using a read-modify-write software routine on the whole CANSTMOB register.
DLC field of the remote or data frame to send. The range of DLC is from 0 up to 8. If DLC field >8 then effective DLC=8. This field is updated with the corresponding value of the remote or data frame received. If the expected DLC differs from the incoming DLC, a DLC warning appears in the CANSTMOB register. 19.11.3 CAN Identifier Tag Registers CANIDT1, CANIDT2, CANIDT3, and CANIDT4 V2.
AT90CAN32/64/128 When a remote or data frame is received, this bit does not operate in the comparison but it is updated with un-predicted values. • Bit 0 – RB0TAG: Reserved Bit 0 Tag RB0 bit of the remote or data frame to send. This tag is updated with the corresponding value of the remote or data frame received. V2.0 part B • Bit 31:3 – IDT28:0: Identifier Tag Identifier field of the remote or data frame to send. This field is updated with the corresponding value of the remote or data frame received.
V2.0 part A • Bit 31:21 – IDMSK10:0: Identifier Mask – 0 - comparison true forced – 1 - bit comparison enabled. • Bit 20:3 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, they must be written to zero when CANIDMn are written. • Bit 2 – RTRMSK: Remote Transmission Request Mask – 0 - comparison true forced – 1 - bit comparison enabled. • Bit 1 – Reserved Bit This bit is reserved for future use.
AT90CAN32/64/128 19.11.6 CAN Data Message Register - CANMSG Bit 7 6 5 4 3 2 1 0 MSG 7 MSG 6 MSG 5 MSG 4 MSG 3 MSG 2 MSG 1 MSG 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value - - - - - - - - CANMSG • Bit 7:0 – MSG7:0: Message Data This register contains the CAN data byte pointed at the page MOb register. After writing in the page MOb register, this byte is equal to the specified message location of the pre-defined identifier + index.
Table 19-2. fclkio (MHz) Examples of CAN Baud Rate Settings for Commonly Frequencies (Continued) CAN Baud Rate (Kbps) Description Sampling Point 1000 67 % (1) 500 75 % 250 75 % 200 75 % 125 75 % 100 75 % 1000 63 % (1) 12.000 500 Registers TQ (µs) Tbit (TQ) Tprs (TQ) Tph1 (TQ) Tph2 (TQ) Tsjw (TQ) CANBT1 CANBT2 CANBT3 0.083333 12 5 3 3 1 0x00 0x08 0x25 x - - - no data- - - 0.166666 12 5 3 3 1 0x02 0x08 0x25 0.250 8 3 2 2 1 0x04 0x04 0x13 0.
AT90CAN32/64/128 Table 19-2. fclkio (MHz) Examples of CAN Baud Rate Settings for Commonly Frequencies (Continued) CAN Baud Rate (Kbps) Description Sampling Point TQ (µs) Segments Tbit (TQ) 1000 6.000 67 % (1) 250 75 % 200 80 % 125 75 % 100 75 % 0.166666 12 4.000 Note: 5 Tsjw (TQ) CANBT1 CANBT2 CANBT3 0x00 0x08 0x25 applicable- - 3 3 1 - - - no data- - - 0.333333 12 5 3 3 1 0x02 0x08 0x25 0.500 8 3 2 2 1 0x04 0x04 0x13 0.
20. Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. 20.1 Overview When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
AT90CAN32/64/128 20.2.2 Analog Comparator Control and Status Register – ACSR Bit 7 6 5 4 3 2 1 0 ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 N/A 0 0 0 0 0 ACSR • Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode.
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 20-1. Table 20-1. ACIS1/ACIS0 Settings ACIS1 ACIS0 Interrupt Mode 0 0 Comparator Interrupt on Output Toggle. 0 1 Reserved 1 0 Comparator Interrupt on Falling Output Edge. 1 1 Comparator Interrupt on Rising Output Edge.
AT90CAN32/64/128 20.3.1 Digital Input Disable Register 1 – DIDR1 Bit 7 6 5 4 3 2 1 0 – – – – – – AIN1D AIN0D Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 DIDR1 • Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set.
21. Analog to Digital Converter - ADC 21.1 Features • • • • • • • • • • • • • • 10-bit Resolution 0.5 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy 13 - 260 µs Conversion Time Up to 76 kSPS at Maximum Resolution Eight Multiplexed Single Ended Input Channels Seven Differential input channels Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 2.
AT90CAN32/64/128 Figure 21-1. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] 0 ADC DATA REGISTER (ADCH/ADCL) ADPS1 ADPS0 ADPS2 ADIF ADSC ADATE ADEN MUX1 REGISTER (ADCSRA) MUX0 MUX2 MUX3 MUX4 REFS0 ADLAR SELECT (ADMUX) REFS1 15 ADC CTRL.
the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V reference voltage may be connected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity. The analog input channel and differential gain are selected by writing to the MUX bits in ADMUX.
AT90CAN32/64/128 Figure 21-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START CLK ADC ADATE ADIF SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. See “Differential Channels” on page 277 for details on differential conversion timing. A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry. The actual sample-and-hold takes place 1.
AT90CAN32/64/128 ? Figure 21-6. ADC Timing Diagram, Auto Triggered Conversion Cycle Number One Conversion 1 2 3 4 5 6 7 8 9 Next Conversi 10 11 12 13 1 2 ADC Clock Trigger Source ADATE ADIF ADCH ADCL ? ? ? Sign and MSB of Resu LSB of Result Sample & Hold Prescaler Reset Prescaler Reset Conversion Complete MUX and REFS Update Figure 21-7.
initiated immediately after the previous conversion completes, and since CKADC2 is high at this time, all automatically started (i.e., all but the first) Free Running conversions will take 14 ADC clock cycles. If differential channels are used and conversions are started by Auto Triggering, the ADC must be switched off between conversions. When Auto Triggering is used, the ADC prescaler is reset before the conversion is started.
AT90CAN32/64/128 21.5.1 ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: • In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection.
another interrupt wakes up the CPU before the ADC conversion is complete, that interrupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed. Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode.
AT90CAN32/64/128 1. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. 2. The AVCC pin on the device should be connected to the digital VCC supply voltage via an LC network as shown in Figure 21-9. 3. Use the ADC noise canceler function to reduce induced noise from the CPU. 4.
Figure 21-10. Offset Error Output Code Ideal ADC Actual AD Offset Error VREF Input Voltage • Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 21-11.
AT90CAN32/64/128 Figure 21-12. Integral Non-linearity (INL) Output Code INL Ideal ADC Actual AD VREF Input Voltage • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 21-13.
For single ended conversion, the result is: V IN ⋅ 1023 ADC = -------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 21-3 on page 286 and Table 21-4 on page 287). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage minus one LSB.
AT90CAN32/64/128 Table 21-2. Correlation Between Input Voltage and Output Codes VADCn Read code Corresponding decimal value VADCm + VREF /GAIN 0x1FF 511 VADCm + 0.999 VREF /GAIN 0x1FF 511 VADCm + 0.998 VREF /GAIN 0x1FE 510 ... ... ... VADCm + 0.001 VREF /GAIN 0x001 1 VADCm 0x000 0 VADCm - 0.001 VREF /GAIN 0x3FF -1 ... ... ... VADCm - 0.999 VREF /GAIN 0x201 -511 VADCm - VREF /GAIN 0x200 -512 Example 1: – ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.
21.8 21.8.1 ADC Register Description ADC Multiplexer Selection Register – ADMUX Bit 7 6 5 4 3 2 1 0 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADMUX • Bit 7:6 – REFS1:0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 21-3.
AT90CAN32/64/128 Table 21-4. Input Channel and Gain Selections MUX4..
21.8.2 ADC Control and Status Register A – ADCSRA Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRA • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
AT90CAN32/64/128 • Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. Table 21-5. 21.8.
• ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on page 283. 21.8.4 ADC Control and Status Register B – ADCSRB Bit 7 6 5 4 3 2 1 0 – ACME – – – ADTS2 ADTS1 ADTS0 Read/Write R R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRB • Bit 7– Reserved Bit This bit is reserved for future use. For compatibility with future devices, it must be written to zero when ADCSRB is written.
AT90CAN32/64/128 21.8.5 Digital Input Disable Register 0 – DIDR0 Bit 7 6 5 4 3 2 1 0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DIDR0 • Bit 7:0 – ADC7D..ADC0D: ADC7:0 Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set.
22. JTAG Interface and On-chip Debug System 22.1 Features • JTAG (IEEE std. 1149.1 Compliant) Interface • Boundary-scan Capabilities According to the IEEE std. 1149.
AT90CAN32/64/128 • TCK: Test Clock. JTAG operation is synchronous to TCK. • TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains). • TDO: Test Data Out. Serial output data from Instruction Register or Data Register (Scan Chains). The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided. When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the TAP controller is in reset.
Figure 22-1.
AT90CAN32/64/128 Figure 22-2. TAP Controller State Diagram 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 1 0 Pause-DR 0 Pause-IR 1 0 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 22.
• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift Register path in the Update-IR state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine. • At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register – Shift-DR state.
AT90CAN32/64/128 • 2 single Program Memory Break Points + 1 Program Memory Break Point with mask (“range Break Point”). • 2 single Program Memory Break Points + 1 Data Memory Break Point with mask (“range Break Point”). A debugger, like the AVR Studio, may however use one or more of these resources for its internal purpose, leaving less flexibility to the end-user. A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Specific JTAG Instructions” on page 297.
22.8 22.8.1 On-chip Debug Related Register in I/O Memory On-chip Debug Register – OCDR Bit 7 6 5 4 3 2 1 0 IDRD/OCDR7 OCDR6 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 OCDR The OCDR Register provides a communication channel from the running program in the microcontroller to the debugger. The CPU can transfer a byte to the debugger by writing to this location.
AT90CAN32/64/128 23. Boundary-scan IEEE 1149.1 (JTAG) 23.1 Features • • • • • 23.2 JTAG (IEEE std. 1149.
23.3.1 Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The Bypass Register may be used to shorten the scan chain on a system when the other devices are to be tested. 23.3.2 Device Identification Register Figure 23-1 shows the structure of the Device Identification Register. Figure 23-1.
AT90CAN32/64/128 23.3.2.4 Device ID The full Device ID is listed in Table 23-4 following the AT90CAN32/64/128 version. Table 23-4. Device ID Version 23.3.3 JTAG Device ID (Hex) AT90CAN32 revision B 0x0958103F AT90CAN64 revision A 0x0968103F AT90CAN128 revision D 0x0978103F Reset Register The Reset Register is a test data register used to reset the part.
23.4.1 EXTEST (0x0) Mandatory JTAG instruction for selecting the Boundary-scan Chain as data register for testing circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output Data, and Input Data are all accessible in the scan chain. For Analog circuits having off-chip connections, the interface between the analog and the digital logic is in the scan chain.
AT90CAN32/64/128 • Shift-DR: The Bypass Register cell between TDI and TDO is shifted. 23.5 23.5.1 Boundary-scan Related Register in I/O Memory MCU Control Register – MCUCR The MCU Control Register contains control bits for general MCU functions.
When no alternate port function is present, the Input Data – ID – corresponds to the PINxn Register value (but ID has no synchronizer), Output Data corresponds to the PORT Register, Output Control corresponds to the Data Direction – DD Register, and the Pull-up Enable – PUExn – corresponds to logic expression PUD · DDxn · PORTxn. Digital alternate port functions are connected outside the dotted box in Figure 23-4 to make the scan chain read the actual pin value.
AT90CAN32/64/128 Figure 23-4. General Port Pin Schematic Diagram See Boundary-scan Description for Details! PUExn PUD D Q DDxn Q CLR WDx RESET OCxn Q Pxn ODxn DATA BUS RDx D PORTxn Q CLR WPx IDxn RESET SLEEP RRx SYNCHRONIZER RPx D Q L Q D Q PINxn Q CLK PUD: PUExn: OCxn: ODxn: IDxn: SLEEP: 23.6.
Figure 23-5. Additional Scan Signal for the Two-wire Interface PUExn OCxn ODxn TWIEN Pxn SRC Slew-rate limited IDxn 23.6.3 Scanning the RESET Pin The RESET pin accepts 3V or 5V active low logic for standard reset operation, and 12V active high logic for High Voltage Parallel programming. An observe-only cell as shown in Figure 23-6 is inserted both for the 3V or 5V reset signal - RSTT, and the 12V reset signal - RSTHV. Figure 23-6.
AT90CAN32/64/128 Figure 23-7.
Figure 23-8. Analog Comparator BANDGAP REFERENCE ACBG ACO AC_IDLE ACME ADCEN ADC MULTIPLEXER OUTPUT Figure 23-9. General Boundary-scan cell Used for Signals for Comparator and ADC To Next ShiftDR Cell EXTEST From Digital Logic/ From Analog Ciruitry To Analog Circuitry/ 0 To Digital Logic 1 0 D Q D Q 1 G From ClockDR UpdateDR Previous Cell Table 23-6.
AT90CAN32/64/128 23.6.6 Scanning the ADC Figure 23-10 shows a block diagram of the ADC with all relevant control and observe signals. The Boundary-scan cell from Figure 23-9 is attached to each of these signals. The ADC need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. Figure 23-10. Analog to Digital Converter VCCREN AREF IREFEN 2.
Table 23-7.
AT90CAN32/64/128 Table 23-7. Boundary-scan Signals for the ADC(1) (Continued) Signal Name Direction as Seen from the ADC Description GNDEN Input Ground the negative input to comparator when true 0 0 HOLD Input Sample & Hold signal. Sample analog signal when low. Hold signal when high. If gain stages are used, this signal must go active when ACLK is high.
Table 23-7. Boundary-scan Signals for the ADC(1) (Continued) Direction as Seen from the ADC Description Input Switch-cap TEST enable. Output from x10 gain stage send out to Port Pin having ADC_4 0 0 ST Input Output of gain stages will settle faster if this signal is high first two ACLK periods after AMPEN goes high. 0 0 VCCREN Input Selects Vcc as the ACC reference voltage.
AT90CAN32/64/128 The recommended values from Table 23-7 are used unless other values are given in the algorithm in Table 23-8. Only the DAC and port pin values of the Scan Chain are shown. The column “Actions” describes what JTAG instruction to be used before filling the Boundary-scan Register with the succeeding columns. The verification should be done on the data scanned out when scanning in the data on the same row in the table. Table 23-8. Algorithm for Using the ADC MUXEN HOLD PRECH PA3. Data PA3.
corresponds to FF1, and PXn. Pullup_enable corresponds to FF2. Bit 2, 3, 4, and 5 of Port C is not in the scan chain, since these pins constitute the TAP pins when the JTAG is enabled. Table 23-9.
AT90CAN32/64/128 Table 23-9. AT90CAN32/64/128 Boundary-scan Order (Continued) Bit Number Signal Name 164 NEGSEL_1 163 NEGSEL_0 162 PASSEN 161 PRECH 160 SCTEST 159 ST 158 VCCREN 157 PE0.Data 156 PE0.Control 155 PE0.Pullup_Enable 154 PE1.Data 153 PE1.Control 152 PE1.Pullup_Enable 151 PE2.Data 150 PE2.Control 149 PE2.Pullup_Enable 148 PE3.Data 147 PE3.Control 146 PE3.Pullup_Enable 145 PE4.Data 144 PE4.Control 143 PE4.Pullup_Enable 142 PE5.Data 141 PE5.
Table 23-9. 316 AT90CAN32/64/128 Boundary-scan Order (Continued) Bit Number Signal Name 126 PB2.Control 125 PB2.Pullup_Enable 124 PB3.Data 123 PB3.Control 122 PB3.Pullup_Enable 121 PB4.Data 120 PB4.Control 119 PB4.Pullup_Enable 118 PB5.Data 117 PB5.Control 116 PB5.Pullup_Enable 115 PB6.Data 114 PB6.Control 113 PB6.Pullup_Enable 112 PB7.Data 111 PB7.Control 110 PB7.Pullup_Enable 109 PG3.Data 108 PG3.Control 107 PG3.Pullup_Enable 106 PG4.Data 105 PG4.
AT90CAN32/64/128 Table 23-9. AT90CAN32/64/128 Boundary-scan Order (Continued) Bit Number Signal Name 88 PD1.Control 87 PD1.Pullup_Enable 86 PD2.Data 85 PD2.Control 84 PD2.Pullup_Enable 83 PD3.Data 82 PD3.Control 81 PD3.Pullup_Enable 80 PD4.Data 79 PD4.Control 78 PD4.Pullup_Enable 77 PD5.Data 76 PD5.Control 75 PD5.Pullup_Enable 74 PD6.Data 73 PD6.Control 72 PD6.Pullup_Enable 71 PD7.Data 70 PD7.Control 69 PD7.Pullup_Enable 68 PG0.Data 67 PG0.Control 66 PG0.
Table 23-9. 318 AT90CAN32/64/128 Boundary-scan Order (Continued) Bit Number Signal Name 50 PC4.Data 49 PC4.Control 48 PC4.Pullup_Enable 47 PC5.Data 46 PC5.Control 45 PC5.Pullup_Enable 44 PC6.Data 43 PC6.Control 42 PC6.Pullup_Enable 41 PC7.Data 40 PC7.Control 39 PC7.Pullup_Enable 38 PG2.Data 37 PG2.Control 36 PG2.Pullup_Enable 35 PA7.Data 34 PA7.Control 33 PA7.Pullup_Enable 32 PA6.Data 31 PA6.Control 30 PA6.Pullup_Enable 29 PA5.Data 28 PA5.Control 27 PA5.
AT90CAN32/64/128 Table 23-9. Bit Number Signal Name 12 PA0.Pullup_Enable Port A 11 PF3.Data Port F 10 PF3.Control 9 PF3.Pullup_Enable 8 PF2.Data 7 PF2.Control 6 PF2.Pullup_Enable 5 PF1.Data 4 PF1.Control 3 PF1.Pullup_Enable 2 PF0.Data 1 PF0.Control 0 PF0.Pullup_Enable Notes: 23.8 AT90CAN32/64/128 Boundary-scan Order (Continued) Comment Module 1. PRIVATE_SIGNAL should always be scanned-in as zero.
24. Boot Loader Support – Read-While-Write Self-Programming The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program.
AT90CAN32/64/128 sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-WhileWrite (NRWW) section. The limit between the RWW- and NRWW sections is given in Table 247 on page 333 and Figure 24-2 on page 323. The main difference between the two sections is: • When erasing or writing a page located inside the RWW section, the NRWW section can be read during the operation.
Figure 24-1. Read-While-Write vs.
AT90CAN32/64/128 Figure 24-2.
• Allow software update in the entire Flash. See Table 24-2 and Table 24-3 for further details. The Boot Lock bits can be set in software and in Serial or Parallel Programming mode, but they can be cleared by a Chip Erase command only. The general Write Lock (Lock Bit mode 2) does not control the programming of the Flash memory by SPM instruction.
AT90CAN32/64/128 grammed, the Reset Vector will always point to the Boot Loader Reset and the fuse can only be changed through the serial or parallel programming interface. Table 24-4. Boot Reset Fuse(1) BOOTRST Note: 24.5.1 Reset Address 1 Reset Vector = Application Reset (address 0x0000) 0 Reset Vector = Boot Loader Reset (see Table 24-6 on page 333) 1.
An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. See “Reading the Fuse and Lock Bits from Software” on page 329 for details. • Bit 2 – PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer.
AT90CAN32/64/128 same page in both the page erase and page write operation. Once a programming operation is initiated, the address is latched and the Z-pointer can be used for other operations. The (E)LPM instruction use the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also bit Z0 of the Z-pointer is used. Figure 24-3.
If only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be rewritten. When using alternative 1, the Boot Loader provides an effective Read-Modify-Write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. If alternative 2 is used, it is not possible to read the old data while loading since the page is already erased.
AT90CAN32/64/128 change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to protect the Boot Loader software from any internal software changes. 24.7.6 Prevent Reading the RWW Section During Self-Programming During Self-Programming (either Page Erase or Page Write), the RWW section is always blocked for reading. The user software itself must prevent that this section is addressed during the self programming operation.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be loaded in the destination register as shown below. Refer to Table 25-5 on page 337 for a detailed description and mapping of the Fuse Low byte.
AT90CAN32/64/128 3. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the SPMCSR Register and thus the Flash from unintentional writes. 24.7.11 Programming Time for Flash when Using SPM The calibrated RC Oscillator is used to time Flash accesses. Table 24-5 shows the typical programming time for Flash accesses from the CPU. Table 24-5. 24.7.
sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256 ldi spmcsrval, (1<
AT90CAN32/64/128 Boot Loader Parameters In Table 24-6 through Table 24-8, the parameters used in the description of the Self-Programming are given.
AT90CAN128 AT90CAN64 AT90CAN32 Variable Value Explanation of Different Variables Used in Figure 24-3 on page 327 and the Mapping to the Z-Pointer(1) Variable Name Device Table 24-8. PCMSB 13 Most significant bit in the program counter. (The program counter is 14 bits PC[13:0]) PAGEMSB 6 Most significant bit which is used to address the words within one page (128 words in a page requires 7 bits PC [6:0]).
AT90CAN32/64/128 25. Memory Programming 25.1 Program and Data Memory Lock Bits The AT90CAN32/64/128 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 25-2. The Lock bits can only be erased to “1” with the Chip Erase command. Table 25-1.
Table 25-2. Lock Bit Protection Modes(1)(2) (Continued) Memory Lock Bits Protection Type 2 1 0 SPM is not allowed to write to the Boot Loader section. 3 0 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section.
AT90CAN32/64/128 Table 25-4. Fuse High Byte (Continued) Fuse High Byte Bit No Description Default Value (6) BOOTSZ1 2 Select Boot Size (see Table 24-6 for details) 0 (programmed)(2) BOOTSZ0 1 Select Boot Size(6) (see Table 24-6 for details) 0 (programmed)(2) BOOTRST 0 Select Reset Vector(7) (see Table 24-6 for details) 1 (unprogrammed) Notes: 1. The SPIEN Fuse is not accessible in serial programming mode. 2. The default value of BOOTSZ1..0 results in maximum Boot Size.
25.3 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked. The three bytes reside in a separate address space. Table 25-6.
AT90CAN32/64/128 Figure 25-1. Parallel Programming +2.7 - +5.5V RDY/BSY PD1 OE PD2 WR PD3 BS1 PD4 XA0 PD5 XA1 PD6 PAGEL PD7 +12 V VCC +2.7 - +5.5V AVCC PB7 - PB0 DA TA RESET BS2 PA0 XTAL1 GND 25.5.2 Pin Mapping Pin Name Mapping Table 25-7. 25.5.3 Signal Name in Programming Mode Pin Name I/O RDY/BSY PD1 O 0: Device is busy programming, 1: Device is ready for new command. OE PD2 I Output Enable (Active low). WR PD3 I Write Pulse (Active low).
Table 25-9. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1). 0 1 Load Data (High or Low data byte for Flash determined by BS1). 1 0 Load Command 1 1 No Action, Idle Table 25-10. Command Byte Bit Coding Command Byte 25.5.
AT90CAN32/64/128 25.6 25.6.1 Parallel Programming Enter Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply power between VCC and GND. 2. Set RESET to “0” and toggle XTAL1 at least six times. 3. Set the Prog_enable pins listed in Table 25-8 on page 339 to “0000” and wait at least 100 ns. 4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after +12V has been applied to RESET, will cause the device to fail entering programming mode. 5.
1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “0001 0000”. This is the command for Write Flash. 4. Give XTAL1 a positive pulse. This loads the command. B: Load Address Low byte 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS1 to “0”. This selects low address. 3. Set DATA = Address low byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address low byte. C: Load Data Low Byte 1. Set XA1, XA0 to “01”. This enables data loading. 2.
AT90CAN32/64/128 1. 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Figure 25-2. Addressing the Flash Which is Organized in Pages(1) PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Note: 1.
25.6.5 Programming the EEPROM The EEPROM is organized in pages, see Table 25-12 on page 340. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to “Programming the Flash” on page 341 for details on Command, Address and Data loading): 1. A: Load Command “0001 0001”. 2. G: Load Address High Byte (0x00 - 0xFF). 3.
AT90CAN32/64/128 25.6.7 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash” on page 341 for details on Command and Address loading): 1. A: Load Command “0000 0011”. 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA. 5. Set OE to “1”. 25.6.
Figure 25-5. Programming the FUSES Waveforms Write Fuse Low byte DATA A C 0x40 DATA XX Write Fuse high byte A C 0x40 DATA XX Write Extended Fuse byte A C 0x40 DATA XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE PAGEL 25.6.11 Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on page 341 for details on Command and Data loading): 1. A: Load Command “0010 0000”. 2. C: Load Data Low Byte.
AT90CAN32/64/128 Figure 25-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read Fuse Low Byte 0 Extended Fuse Byte 1 0 DATA BS2 Lock Bits 0 Fuse High Byte 1 1 BS1 BS2 25.6.13 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” on page 341 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte (0x00 - 0x02). 3. Set OE to “0”, and BS1 to “0”.
Figure 25-7. Serial Programming and Verify(1) +2.7 - +5. VCC PDI +2.7 - +5. PE0 PDO PE1 SCK PB1 AVCC XTAL1 RESET GND Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction.
AT90CAN32/64/128 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”. 2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI. 3.
grammed without chip erasing the device. In this case, data polling cannot be used for the value 0xFF, and the user will have to wait at least tWD_EEPROM before programming the next byte. See Table 25-14 for tWD_EEPROM value. Table 25-14. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FUSE 4.5 ms tWD_FLASH 4.5 ms tWD_EEPROM 9.0 ms tWD_ERASE 9.0 ms Figure 25-8.
AT90CAN32/64/128 Table 25-15. Serial Programming Instruction Set (Continued) Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction Instruction Format(1) Byte 1 Byte 2(2) Byte 3 Byte4 Operation(1) Load EEPROM Memory Page (page access) 1100 0001 0000 0000 0000 0bbb iiii iiii Write EEPROM Memory Page (page access) 1100 0010 000x aaaa bbbb b000 xxxx xxxx Write EEPROM page at address a:b.
the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be dedicated for this purpose. During programming the clock frequency of the TCK Input must be less than the maximum frequency of the chip. The System Clock Prescaler can not be used to divide the TCK Clock Input into a sufficiently low frequency. As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers. 25.9.
AT90CAN32/64/128 25.9.1.1 AVR_RESET (0xC) The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset mode. The TAP controller is not reset by this instruction. The one bit Reset Register is selected as data register. Note that the reset will be active as long as there is a logic “one” in the Reset Chain. The output from this chain is not latched. The active states are: • Shift-DR: The Reset Register is shifted by the TCK input. 25.9.1.
• Capture-DR: The content of the selected Flash byte is captured into the Flash Data Byte Register. The AVR automatically alternates between reading the low and the high byte for each new Capture-DR state, starting with the low byte for the first Capture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte.
AT90CAN32/64/128 25.9.2.3 Programming Command Register The Programming Command Register is a 15-bit register. This register is used to serially shift in programming commands, and to serially shift out the result of the previous command, if any. The JTAG Programming Instruction Set is shown in Table 25-16. The state sequence when shifting in the programming commands is illustrated in Figure 25-12. Figure 25-11.
Table 25-16. JTAG Programming Instruction (Continued) Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence(1)(2) TDO Sequence(1)(2) Notes 2g. Write Flash Page 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (3) 2h. Poll for Page Write Complete 0110111_00000000 xxxxxox_xxxxxxxx (4) 3a.
AT90CAN32/64/128 Table 25-16. JTAG Programming Instruction (Continued) Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence(1)(2) TDO Sequence(1)(2) Notes 6f. Write Fuse High Byte 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (3) 6g. Poll for Fuse Write Complete 0110111_00000000 xxxxxox_xxxxxxxx (4) 6h.
Table 25-16. JTAG Programming Instruction (Continued) Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence(1)(2) TDO Sequence(1)(2) 10b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 10c. Read Calibration Byte 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 11a. Load No Operation Command 0100011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx Notes: Notes 1.
AT90CAN32/64/128 Figure 25-12. State Machine Sequence for Changing/Reading the Data Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 1 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 25.9.2.
ture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page. Figure 25-13.
AT90CAN32/64/128 25.9.3.3 Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS. 2. Start Chip Erase using programming instruction 1a. 3. Poll for Chip Erase complete using programming instruction 1b, or wait for tWLRH_CE (refer to Table 26-15 on page 381). 25.9.3.4 Programming the Flash 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load address High byte using programming instruction 2b. 4.
4. Enter JTAG instruction PROG_PAGEREAD. 5. Read the entire page (or Flash) by shifting out all instruction words in the page (or Flash), starting with the LSB of the first instruction in the page (Flash) and ending with the MSB of the last instruction in the page (Flash). The Capture-DR state both captures the data from the Flash, and also auto-increments the program counter after each word is read. Note that Capture-DR comes before the shift-DR state.
AT90CAN32/64/128 25.9.3.9 Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Lock bit write using programming instruction 7a. 3. Load data using programming instructions 7b. A bit value of “0” will program the corresponding lock bit, a “1” will leave the lock bit unchanged. 4. Write Lock bits using programming instruction 7c. 5. Poll for Lock bit write complete using programming instruction 7d, or wait for tWLRH (refer to Table 26-15 on page 381). 25.9.3.
26. Decoupling Capacitors The operating frequency (i.e. system clock) of the processor determines in 95% of cases the value needed for microcontroller decoupling capacitors. The hypotheses used as first evaluation for decoupling capacitors are: • The operating frequency (fop) supplies itself the maximum peak levels of noise. The main peaks are located at fop and 2 • fop. • An SMC capacitor connected to 2 micro-vias on a PCB has the following characteristics: – 1.
AT90CAN32/64/128 27. Electrical Characteristics (1) 27.1 Absolute Maximum Ratings* Automotive Operating Temperature..............– 40°C to +125°C Storage Temperature ....................................– 65°C to +150°C Voltage on any Pin except RESET with respect to Ground .............................. – 0.5V to VCC+0.5V Voltage on RESET with respect to Ground.... – 0.5V to +13.0V Voltage on VCC with respect to Ground............. – 0.5V to 6.
27.2 DC Characteristics(1) TA = -40°C to +125°C, VCC = 2.7V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min. VIL Input Low Voltage Except XTAL1 and RESET pins VIL1 Input Low Voltage VIL2 Max. Units – 0.5 0.2 Vcc (2) V XTAL1 pin - External Clock Selected – 0.5 0.1 Vcc (2) V Input Low Voltage RESET pin – 0.5 0.2 Vcc (2) V VIH Input High Voltage Except XTAL1 and RESET pins 0.6 Vcc (3) Vcc + 0.5 V VIH1 Input High Voltage XTAL1 pin - External Clock Selected 0.
AT90CAN32/64/128 TA = -40°C to +125°C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Min. IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 – 50 Analog Comparator Propagation Delay Common Mode Vcc/2 VCC = 2.7V 170 ns tACID VCC = 5.0V 180 ns Notes: Typ. Max. Units 50 nA 1.
External Clock Drive Table 27-1. 27.4 VCC = 2.7 - 5.5V VCC = 4.5 - 5.5V Min. Max. Min. Max. 0 8 0 16 Symbol Parameter Units 1/tCLCL Oscillator Frequency tCLCL Clock Period 125 62.5 ns tCHCX High Time 50 25 ns tCLCX Low Time 50 25 ns tCLCH Rise Time 1.6 0.5 µs tCHCL Fall Time 1.6 0.5 µs ∆tCLCL Change in period from one clock cycle to the next 2 2 % MHz Maximum Speed vs. VCC Maximum frequency is depending on VCC. As shown in Figure 27-2.
AT90CAN32/64/128 Figure 27-2. Maximum Frequency vs. VCC, AT90CAN32/64/128 Frequency 16 MHz 8 MHz Safe Operating Area Voltag 2.7V 4.5V 5.
27.5 Two-wire Serial Interface Characteristics Table 27-3 describes the requirements for devices connected to the Two-wire Serial Bus. The AT90CAN32/64/128 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 27-3. Table 27-3. Two-wire Serial Bus Requirements Symbol Parameter VIL VIH tr Input Low-voltage – 0.5 0.3 Vcc V Input High-voltage 0.7 Vcc Vcc + 0.5 V – V 0 0.4 V 20 + 0.1Cb 300 ns 20 + 0.
AT90CAN32/64/128 2. Required only for fSCL > 100 kHz. 3. Cb = capacitance of one bus line in pF. 4. fCK = CPU clock frequency 5. This requirement applies to all AT90CAN32/64/128 Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general fSCL requirement. 6.
Table 27-4. SPI Timing Parameters (Continued) Description Mode Min. 13 Setup Slave 10 14 Hold Slave tck 15 SCK to out Slave 16 SCK to SS high Slave 17 SS high to tri-state Slave 18 SS low to SCK Slave Note: Typ. Max. 15 ns 20 10 2 • tck In SPI Programming mode the minimum SCK high/low period is: - 2 tCLCL for fCK < 12 MHz - 3 tCLCL for fCK >12 MHz Figure 27-4.
AT90CAN32/64/128 27.7 CAN Physical Layer Characteristics Only pads dedicated to the CAN communication belong to the physical layer. Table : CAN Physical Layer Characteristics (1) Parameter 1 2 Notes: TxCAN output delay RxCAN input delay Condition Min. Max. Units Vcc=2.7 V Load=20 pF VOL/VOH=VCC/2 9 Vcc=4.5 V Load=20 pF VOL/VOH=VCC/2 5.3 Vcc=2.7 V VIL/VIH=VCC/2 9+ Vcc=4.5 V VIL/VIH=VCC/2 7.2 + 1 ns / fCLKIO(2) 1 / fCLKIO(2) 1. From design simulations. 2. Metastable immunity flip-flop.
27.8 ADC Characteristics((1) Table 27-5. Symbol ADC Characteristics, Single Ended Channels Min(2) Typ(2) Parameter Condition Resolution Single Ended Conversion 10 Single Ended Conversion VREF = 4V, Vcc = 4V ADC clock = 200 kHz 1.5 Absolute accuracy (Included INL, DNL, Quantization Error, Gain and Offset Error) Single Ended Conversion VREF = 4V, Vcc = 4V Single Ended Conversion VREF = 4V, Vcc = 4V ADC clock = 200 kHz Noise Reduction Mode 1.
AT90CAN32/64/128 Table 27-6.
27.9 External Data Memory Characteristics(1) Table 27-7. External Data Memory Characteristics, VCC = 4.5 - 5.5 Volts, No Wait-state Symbol Parameter 0 1/tCLCL Oscillator Frequency 1 tLHLL ALE Pulse Width 8 MHz Oscillator Min. Max. 115 Variable Oscillator Min. Max. 0.0 16 Unit MHz 1.0 tCLCL – 10 ns (2) 2 tAVLL Address Valid A to ALE Low 57.
AT90CAN32/64/128 Table 27-9. External Data Memory Characteristics, VCC = 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0 (1) 8 MHz Oscillator Variable Oscillator Symbol Parameter 0 1/tCLCL Oscillator Frequency 10 tRLDV Read Low to Data Valid 12 tRLRH RD Pulse Width 365 3.0 tCLCL – 10 ns 15 tDVWH Data Valid to WR High 375 3.0 tCLCL ns 16 tWLWH WR Pulse Width 365 3.0 tCLCL – 10 ns Min. Max. Min. Max. 0.0 16 325 Unit MHz 3.0 tCLCL – 50 ns Table 27-10.
Table 27-11. External Data Memory Characteristics, VCC = 2.7 - 5.5 Volts, No Wait-state (Continued)(1) Symbol Parameter 11 tRHDX Data Hold After RD High 12 tRLRH 13 4 MHz Oscillator Min. Max. Variable Oscillator Min. Max. Unit 0 0 ns RD Pulse Width 235 1.0 tCLCL – 15 ns tDVWL Data Setup to WR Low 105 0.5 tCLCL – 20 (2) ns 14 tWHDX Data Hold After WR High 235 1.0 tCLCL – 15 ns 15 tDVWH Data Valid to WR High 250 1.0 tCLCL ns 16 tWLWH WR Pulse Width 235 1.
AT90CAN32/64/128 Table 27-14. External Data Memory Characteristics, VCC = 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1 (1) 4 MHz Oscillator Variable Oscillator Symbol Parameter 0 1/tCLCL Oscillator Frequency 10 tRLDV Read Low to Data Valid 12 tRLRH RD Pulse Width 735 3.0 tCLCL – 15 ns 14 tWHDX Data Hold After WR High 485 2.0 tCLCL – 15 ns 15 tDVWH Data Valid to WR High 750 3.0 tCLCL ns 16 tWLWH WR Pulse Width 735 3.0 tCLCL – 15 ns Notes: Min. Max. Min. Max. 0.0 8 690 3.
Figure 27-7. External Memory Timing (SRWn1 = 0, SRWn0 = 1) T1 T2 T3 T4 T5 System Clock (CLK CPU ) 1 ALE 4 7 A15:8 Prev. addr. Address 15 3a DA7:0 Prev. data Address 13 Data XX 14 16 6 Write 2 WR 9 3b DA7:0 (XMBK = 0) Data 5 Read Address 11 10 8 12 RD Figure 27-8. External Memory Timing (SRWn1 = 1, SRWn0 = 0) T1 T2 T3 T4 T5 T6 System Clock (CLK CPU ) 1 ALE 4 7 Address A15:8 Prev. addr. 15 DA7:0 Prev.
AT90CAN32/64/128 Figure 27-9. External Memory Timing (SRWn1 = 1, SRWn0 = 1)(1) T1 T2 T3 T6 T5 T4 T7 System Clock (CLK CPU ) 1 ALE 4 7 Address A15:8 Prev. addr. 15 DA7:0 Prev. data 3a Address 13 XX Write 2 Data 14 16 6 WR 9 3b Address 11 Data 5 Read DA7:0 (XMBK = 0) 10 8 12 RD Note: 1. The ALE pulse in the last period (T4-T7) is only present if the next instruction accesses the RAM (internal or external). 27.10 Parallel Programming Characteristics Figure 27-10.
Figure 27-11. Parallel Programming Timing, Loading Sequence with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) LOAD DATA LOAD DATA (HIGH BYTE) LOAD DATA (LOW BYTE) tXLPH tXLXH LOAD ADDRESS (LOW BYTE) tPLXH XTAL1 BS1 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 27-10 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation. Figure 27-12.
AT90CAN32/64/128 Note: 1. The timing requirements shown in Figure 27-10 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation. Table 27-15. Parallel Programming Characteristics, VCC = 5V ± 10% (1) Symbol Parameter Min. VPP Programming Enable Voltage 11.
28.
AT90CAN32/64/128 Address Name (0xBE) Reserved (0xBD) Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE page 211 (0xBB) TWDR TWDR7 TWDR6 TWDR5 TWDR4 TWDR3 TWDR2 TWDR1 TWDR0 page 213 (0xBA) TWAR TWAR6 TWAR5 TWAR4 TWAR3 TWAR2 TWAR1 TWAR0 TWGCE page 213 (0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 page 212 (0xB8) TWBR TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 page 211
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 page 286 (0x7B) ADCSRB – ACME – – – ADTS2 ADTS1 ADTS0 page 290, 268 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 page 288 (0x79) ADCH - / ADC9 - / ADC8 - / ADC7 - / ADC6 - / ADC5 - / ADC4 ADC9 / ADC3 ADC8 / ADC2 page 289 (0x78) ADCL ADC7 / ADC1 ADC6 / ADC0 ADC5 / - ADC4 / - ADC3 / - ADC2 / - ADC1 / - ADC0 / pag
AT90CAN32/64/128 Address Name 0x1A (0x3A) Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x19 (0x39) Reserved 0x18 (0x38) 0x17 (0x37) TIFR3 – – ICF3 – OCF3C OCF3B TIFR2 – – – – – – OCF3A TOV3 page 143 OCF2A TOV2 0x16 (0x36) TIFR1 – – ICF1 – OCF1C page 161 OCF1B OCF1A TOV1 0x15 (0x35) TIFR0 – – – – page 143 – – OCF0A TOV0 0x14 (0x34) PORTG – – – page 112 PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 0x13 (0x33) DDRG – – page 92 – D
29. AT90CAN32/64/128 Typical Characteristics • The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. • The power consumption in Power-down mode is independent of clock selection.
AT90CAN32/64/128 Figure 29-2. Active Supply Current vs. Frequency (1 - 16 MHz) IDLE S UP P LY CURRENT vs . FREQUENCY Te mpe ra ture = 125˚C 25 20 5.5 V ICC (mA) 5.0 V 15 4.5 V 10 3.3 V 3.0 V 2.7 V 5 0 0 2 4 6 8 10 12 14 16 18 20 Fre que nc y (MHz ) Figure 29-3. Active Supply Current vs. Vcc (Internal RC Oscillator 8 MHz) ACTIVE S UP P LY CURRENT vs . VC C INTERNAL RC OSCILLATOR, 8 MHz 16 125 85 25 -40 14 ˚C ˚C ˚C ˚C 12 ICC (mA) 10 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.
Figure 29-4. Active Supply Current vs. Vcc (Internal RC Oscillator 1 MHz) ACTIVE S UP P LY CURRENT vs . V C C INTERNAL RC OSCILLATOR, 1 MHz 3500 125 ˚C 85 ˚C 25 ˚C -40 ˚C 3000 ICC (uA) 2500 2000 1500 1000 500 0 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 29.2 Idle Supply Current Figure 29-5. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) - Temperature = 25°C IDLE S UP P LY CURRENT vs . LOW FREQUENCY Te mpe ra ture = 25˚C 1.2 1 5.5 V 5.0 V ICC (mA) 0.8 4.5 V 0.6 3.3 V 3.0 V 2.7 V 0.4 0.2 0 0 0.
AT90CAN32/64/128 Figure 29-6. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) - Temperature = 125°C IDLE S UP P LY CURRENT vs . LOW FREQUENCY Te mpe ra ture = 125˚C 1.2 5.5 V 1 5.0 V ICC (mA) 0.8 4.5 V 0.6 3.3 V 3.0 V 2.7 V 0.4 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Fre que nc y (MHz ) Figure 29-7. dle Supply Current vs. Frequency (1 - 16 MHz) - Temperature = 25°C IDLE S UP P LY CURRENT vs . FREQUENCY Te mpe ra ture = 25˚C 20 5.5 V 18 5.0 V 16 4.
Figure 29-8. dle Supply Current vs. Frequency (1 - 16 MHz) - Temperature = 125°C IDLE S UP P LY CURRENT vs . FREQUENCY Te mpe ra ture = 125˚C 25 20 5.5 V ICC (mA) 5.0 V 15 4.5 V 10 3.3 V 3.0 V 2.7 V 5 0 0 2 4 6 8 10 12 14 16 18 20 Fre que nc y (MHz ) Figure 29-9. Idle Supply Current vs. Vcc (Internal RC Oscillator 8 MHz) IDLE S UP P LY CURRENT vs . VC C INTERNAL RC OSCILLATOR, 8 MHz 18 125 85 25 -40 16 14 ˚C ˚C ˚C ˚C ICC (mA) 12 10 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.
AT90CAN32/64/128 Figure 29-10. Idle Supply Current vs. Vcc (Internal RC Oscillator 1 MHz) IDLE S UP P LY CURRENT vs . V C C INTERNAL RC OSCILLATOR, 1 MHz 1.4 125 85 25 -40 1.2 ˚C ˚C ˚C ˚C ICC (mA) 1 0.8 0.6 0.4 0.2 0 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 29-11. Idle Supply Current vs. Vcc (32 kHz Watch Crystal) IDLE SUPPLY CURRENT vs. Vcc (32 KHz Watch Crystal) 60 50 Icc (uA) 40 30 25°C 20 10 0 2.5 3 3.5 4 4.5 5 5.
29.3 Power-down Supply Current Figure 29-12. Power-down Supply Current vs. Vcc (Watchdog Timer Disabled) - Temp. = 25°C P OWER-DOWN S UP P LY CURRENT vs . VC C WATCHDOG TIMER DISABLED 8 25 ˚C 7 6 ICC (uA) 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 29-13. Power-down Supply Current vs. Vcc (Watchdog Timer Disabled) - Temp.= 125°C P OWER-DOWN S UP P LY CURRENT vs . VC C WATCHDOG TIMER DISABLED 120 125 ˚C 100 ICC (uA) 80 60 40 20 85 ˚C 25 ˚C -40 ˚C 0 2.5 3 3.5 4 4.5 5 5.
AT90CAN32/64/128 Figure 29-14. Power-down Supply Current vs. Vcc (Watchdog Timer Enabled) - Temp.= 25°C P OWER-DOWN S UP P LY CURRENT vs . VC C WATCHDOG TIMER ENABLED 25 25 ˚C ICC (uA) 20 15 10 5 0 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 29-15. Power-down Supply Current vs. Vcc (Watchdog Timer Enabled) - Temp.= 125°C P OWER-DOWN S UP P LY CURRENT vs . VC C WATCHDOG TIMER ENABLED 140 125 ˚C 120 ICC (uA) 100 80 60 40 85 ˚C 25 ˚C -40 ˚C 20 0 2.5 3 3.5 4 4.5 5 5.
29.4 Power-save Supply Current Figure 29-16. Power-save Supply Current vs. Vcc (Watchdog Timer Disabled) P OWER-SAVE S UP P LY CURRENT vs . V C C (WATCHDOG TIMER DIS ABLED) 50 45 125 ˚C 40 35 ICC (uA) 30 25 20 15 10 25 ˚C 5 0 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 29.5 Pin Pull-up Figure 29-17. I/O Pin Pull-up Resistor Current vs. Input Voltage (Vcc = 5V) I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE V CC=5.0V 160 140 -40 ˚C 120 125 ˚C IOP (uA) 100 80 60 40 20 0 0 0.5 1 1.5 2 2.
AT90CAN32/64/128 Figure 29-18. I/O Pin Pull-up Resistor Current vs. Input Voltage (Vcc = 2.7V) I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE V CC=3.0V 90 80 -40 ˚C 70 IOP (uA) 60 125 ˚C 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 V OP (V) Figure 29-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage (Vcc = 5V) RES ET P ULL-UP RES IS TOR CURRENT vs . RES ET P IN VOLTAGE V CC=5.0V 120 100 IRE S E T (uA) 80 60 40 20 125 ˚C -40 ˚C 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 29-20. Reset Pull-up Resistor Current vs. Reset Pin Voltage (Vcc = 2.7V) RES ET P ULL-UP RES IS TOR CURRENT vs . RES ET P IN VOLTAGE V CC=2.7V 60 50 IRES ET (uA) 40 30 20 10 125 ˚C 0 0 0.5 1 1.5 2 2.5 -40 ˚C 3 V RE S E T (V) 29.6 Pin Driver Strength Figure 29-21. I/O Pin Output Voltage vs. Source Current (Vcc = 5V) I/O P IN OUTP UT VOLTAGE vs . S OURCE CURRENT V CC=5.0V 5.1 5 4.9 V OH (V) 4.8 4.7 4.6 -40 ˚C 4.5 25 ˚C 85 ˚C 125 ˚C 4.4 4.
AT90CAN32/64/128 Figure 29-22. I/O Pin Output Voltage vs. Source Current (Vcc = 2.7V) I/O P IN OUTP UT VOLTAGE vs . S OURCE CURRENT V CC=3.0V 3.5 3 V OH (V) 2.5 -40 25 85 125 2 ˚C ˚C ˚C ˚C 1.5 1 0.5 0 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) Figure 29-23. I/O Pin Output Voltage vs. Sink Current (Vcc = 5V) I/O P IN OUTP UT VOLTAGE vs . S INK CURRENT V CC=5.0V 0.7 125 ˚C V OL (V) 0.6 85 ˚C 0.5 25 ˚C 0.4 -40 ˚C 0.3 0.2 0.
Figure 29-24. I/O Pin Output Voltage vs. Sink Current (Vcc = 2.7V) I/O P IN OUTP UT VOLTAGE vs . S INK CURRENT V CC=3.0V 1.2 125 ˚C 1 85 ˚C V OL (V) 0.8 25 ˚C 0.6 -40 ˚C 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) 29.7 Pin Thresholds and Hysteresis Figure 29-25. I/O Input Threshold Voltage vs. Vcc (VIH, I/O Pin Read as “1”) I/O P IN INP UT THRES HOLD VOLTAGE vs . VC C VIH, IO PIN READ AS '1' 3.5 3 Thres hold (V) 2.5 125 ˚C -40 ˚C 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
AT90CAN32/64/128 Figure 1. I/O Input Threshold Voltage vs. Vcc (VIL, I/O Pin Read as “0”) I/O P IN INP UT THRES HOLD VOLTAGE vs . V C C VIL, IO PIN READ AS '0' Thres hold (V) 2 -40 ˚C 125 ˚C 1.5 1 0.5 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 29.8 BOD Thresholds and Analog Comparator Offset Figure 29-26. BOD Thresholds vs. Temperature (BOD level is 4.1V) BOD THRES HOLDS vs . TEMP ERATURE BOD = 4.1V 4.5 Thres hold (V) 4.3 1 4.1 0 3.9 3.7 3.
Figure 29-27. BOD Thresholds vs. Temperature (BOD level is 2.7V) BOD THRES HOLDS vs . TEMP ERATURE BOD = 2.7V 3 2.8 Thres hold (V) 1 0 2.6 2.4 2.2 2 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Te mpe ra ture (C) Figure 29-28. Bandgap Voltage vs. Operating Voltage BANDGAP VOLTAGE vs . V C C Bandgap Voltage (V) 1.2 1.15 1.1 125 ˚C -40 ˚C 1.05 1 2.5 3 3.5 4 4.5 5 5.
AT90CAN32/64/128 29.9 Internal Oscillator Speed Figure 29-29. Watchdog Oscillator Frequency vs. Operating Voltage WATCHDOG OS CILLATOR FREQUENCY vs . OP ERATING VOLTAGE 1400 1350 -40 25 85 125 1300 FRC (kHz ) 1250 ˚C ˚C ˚C ˚C 1200 1150 1100 1050 1000 950 900 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 29-30. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED XXXMHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE 8.15 5.0 V 8.1 FRC (MHz) 8.05 8 7.95 7.9 7.85 7.8 7.
Figure 29-31. Calibrated 8 MHz RC Oscillator Frequency vs. Operating Voltage CALIBRATED XXXMHz RC OS CILLATOR FREQUENCY vs . OP ERATING VOLTAGE 8.8 8.6 FRC (MHz) 8.4 125 ˚C 85 ˚C 25 ˚C 8.2 8 -40 ˚C 7.8 7.6 7.4 7.2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 29-32. Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value INT RC OS CILLATOR FREQUENCY vs .
AT90CAN32/64/128 29.10 Current Consumption of Peripheral Units Figure 29-33. Brownout Detector Current vs. Operating Voltage BROWNOUT DETECTOR CURRENT vs . VC C 30 125 85 25 -40 25 ICC (uA) 20 ˚C ˚C ˚C ˚C 15 10 5 0 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 29-34. AREF External Reference Current vs. Operating Voltage AREF CURRENT WITH ADC AT 1MHz vs . VC C 200 125 ˚C -40 ˚C 175 ICC (uA) 150 125 100 75 50 2.5 3 3.5 4 4.5 5 5.
Figure 29-35. Analog Comparator Current vs. Operating Voltage ANALOG COMP ARATOR CURRENT vs . VC C 200 180 160 ICC (uA) 140 120 100 80 60 125 ˚C -40 ˚C 40 20 0 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 29-36. Programming Current vs. Operating Voltage EEP ROM WRITE CURRENT vs . Vcc Ext Clk 25 -40 ˚C 20 ICC (mA) 25 ˚C 15 85 ˚C 125 ˚C 10 5 0 2.5 3 3.5 4 4.5 5 5.
AT90CAN32/64/128 29.11 Current Consumption in Reset and Reset Pulse Width Figure 29-37. Reset Supply Current vs. Operating Voltage (0.1 - 1.0 MHz) (Excluding Current Through the Reset Pull-up) RES ET S UP P LY CURRENT vs . VC C EXCLUDING CURRENT THROUGH THE RESET PULLUP 0.35 0.3 5.5 V 0.25 5.0 V ICC (mA) 4.5 V 0.2 4.0 3.6 3.3 3.0 2.7 0.15 0.1 V V V V V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Fre que nc y (MHz ) Figure 29-38. Reset Supply Current vs.
Figure 29-39. Minimum Reset Pulse Width vs. Operating Voltage RES ET P ULS E WIDTH vs . VC C 1400 1200 Puls e width (ns ) 1000 800 600 125 85 25 -40 400 ˚C ˚C ˚C ˚C 200 0 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 29.12 Analog To Digital Converter Figure 29-40. Integral Non Linearity (INL), Single Ended Analog to Digital Converter - Integral Non Linearity INL Single Ende d, Vc c = 4V, Vre f = 4V 0.68 0.66 LSB 0.64 0.62 0.6 0.58 0.56 0.
AT90CAN32/64/128 Figure 29-41. Integral Non Linearity (INL), Differential Inputs Analog to Digital Converter - Integral Non Linearity INL Diffe re ntia l Inputs , Vc c = 4V, Vre f = 4V 0.6 0.5 LSB 0.4 0.3 Diff x1 0.2 Diff x200 0.1 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Te mpe ra ture Figure 29-42. Differential Non Linearity (DNL), Single Ended Analog to Digital Converter - Differential Non Linearity DNL Single Ende d, Vc c = 4V, Vre f = 4V 0.5 0.48 0.46 0.
Figure 29-43. Differential Non Linearity (DNL), Differential Inputs Analog to Digital Converter - Differential Non Linearity DNL Diffe re ntia l Inputs , Vc c = 4V, Vre f = 4V 0.45 0.4 0.35 LSB 0.3 Diff x1 0.25 Diff x200 0.2 0.15 0.1 0.05 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Te mpe ra ture Figure 29-44. OFFSET, Single Ended Analog to Digital Converter - OFFS ET Single Ende d, Vc c = 4V, Vre f = 4V 1.4 1.2 LSB 1 0.8 0.6 0.4 0.
AT90CAN32/64/128 Figure 29-45. OFFSET, Differential Inputs Analog to Digital Converter - OFFS ET Diffe re ntia l Inputs , Vc c = 4V, Vre f = 4V 0.34 Diff x200 0.32 Diff x1 LSB 0.3 0.28 0.26 0.24 0.22 0.2 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Te mpe ra ture Figure 29-46. GAIN, Single Ended Analog to Digital Converter - GAIN Single Ende d, Vc c = 4V, Vre f = 4V -0.2 LSB -0.4 -0.6 -0.8 -1 -1.
Figure 29-47. GAIN, Differential Inputs Analog to Digital Converter - GAIN Diffe re ntia l Inputs , Vc c = 5V, Vre f = 4V 0 -0.2 -0.4 -0.6 Diff x200 LSB -0.8 Diff x1 -1 -1.2 -1.4 -1.6 -1.8 -2 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Te mpe ra ture Figure 29-48. Absolute Accuracy (TUE), Single Ended Analog to Digital Converter - Abs olute Accuracy (TUE) Single Ende d, Vc c = 4V, Vre f = 4V 2 1.9 1.8 1.7 LSB 1.6 1.5 1.4 1.3 1.2 1.
AT90CAN32/64/128 Figure 29-49. Absolute Accuracy (TUE), Differential Inputs Analog to Digital Converter - Abs olute Accuracy (TUE) Differential Inputs , Vcc = 5V, Vref = 4V 1.6 1.4 1.2 LSB 1 Diff x1 0.8 Diff x200 0.6 0.4 0.
30.
AT90CAN32/64/128 Mnemonics Operands Description Operation Flags #Clocks BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(
Mnemonics Operands Description Operation Flags #Clocks IN Rd, P In Port Rd ← P None 1 OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 None 1 MCU CONTROL INSTRUCTIONS 416 NOP No Operation SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr.
AT90CAN32/64/128 31. Ordering Information (1) Speed (MHz(4)) Power Supply (V) Package(2)(3) Operation Range AT90CAN32-15AT 16 2.7 - 5.5 A2 64 Automotive (-40° to +85°C) AT90CAN32-15AT1 16 2.7 - 5.5 A2 64 Automotive (-40° to +105°C) Ordering Code AT90CAN32-15AZ 16 2.7 - 5.5 A2 64 Automotive (-40° to +125°C) AT90CAN32-15MT 16 2.7 - 5.5 Z64-1 Automotive (-40° to +85°C) AT90CAN32-15MT1 16 2.7 - 5.5 Z64-1 Automotive (-40° to +105C) AT90CAN32-15MZ 16 2.7 - 5.
32.
AT90CAN32/64/128 32.
33. Errata 33.1 33.1.1 Errata Summary AT90CAN128 RevD (Date code ≥ 0107) • CAN transmission after 3-bit intermission • Asynchronous Timer-2 wakes up without interrupt • SPI programming timing 33.1.2 AT90CAN32 RevB (Date code ≥ 0107) • CAN transmission after 3-bit intermission • Asynchronous Timer-2 wakes up without interrupt • SPI programming timing 33.1.
AT90CAN32/64/128 4. CAN acknowledge error in 3-sample mode with prescaler =1 Some acknowledge errors can occur when the clock prescaler = 1 (BRP[5..0] = 0 in CANBTR1 register) and the SMP bit is set (CANBTR3[0] = 1 in CANBTR3 register). That can result in a reduction of the maximum length of the CAN bus. Problem fix / workaround If BRP[5..0]=0 use SMP=0. 3.
__interrupt void can_int_handler(void) { if ((CANSIT1 & 0x40) == 0x40 ) /* MOb14 interrupt (SIT14=1) */ { CANPAGE = (0x0E << 4); /* select MOb14 */ CANSTMOB = 0x00; /* reset MOb14 status */ CANCDMOB = 0x88; /* reception enable */ } ........ ........ } 2. Asynchronous Timer-2 wakes up without interrupt The asynchronous timer can wake from sleep without giving interrupt.
AT90CAN32/64/128 34. Datasheet Revision History for AT90CAN32/64/128 Please note that the referring page numbers in this section are referring to this document. The referring revision in this section are referring to the document revision. 34.1 7682A - 01/07 1. Rev A. document creation. 34.2 7682B - 09/07 1. ADC conversion time updated. See “Analog to Digital Converter - ADC” on page 272 2. CAN filter values corrected. See “Acceptance Filter” on page 244. 34.3 7682C - 04/08 1. Updated Errata list. 2.
1 Description ............................................................................................... 2 1.1 Comparison Between AT90CAN32, AT90CAN64 and AT90CAN128 ................2 1.2 Part Description ..................................................................................................2 1.3 Disclaimer ...........................................................................................................3 1.4 Automotive Quality Grade .........................................
AT90CAN32/64/128 5.10 6 7 8 9 System Clock Prescaler ....................................................................................44 Power Management and Sleep Modes ................................................. 46 6.1 Idle Mode ..........................................................................................................47 6.2 ADC Noise Reduction Mode .............................................................................47 6.3 Power-down Mode .......................
12.9 8-bit Timer/Counter Register Description ........................................................109 13 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) ........... 113 13.1 Features ..........................................................................................................113 13.2 Overview .........................................................................................................113 13.3 Accessing 16-bit Registers ............................................
AT90CAN32/64/128 17.2 Overview .........................................................................................................176 17.3 Dual USART ...................................................................................................176 17.4 Clock Generation ............................................................................................178 17.5 Serial Frame ...................................................................................................180 17.
20.1 Overview .........................................................................................................268 20.2 Analog Comparator Register Description .......................................................268 20.3 Analog Comparator Multiplexed Input .............................................................270 21 Analog to Digital Converter - ADC ...................................................... 272 21.1 Features ...............................................................
AT90CAN32/64/128 24.3 Read-While-Write and No Read-While-Write Flash Sections .........................320 24.4 Boot Loader Lock Bits .....................................................................................323 24.5 Entering the Boot Loader Program .................................................................324 24.6 Addressing the Flash During Self-Programming .............................................326 24.7 Self-Programming the Flash ..........................................
29.6 Pin Driver Strength ..........................................................................................398 29.7 Pin Thresholds and Hysteresis .......................................................................400 29.8 BOD Thresholds and Analog Comparator Offset ............................................401 29.9 Internal Oscillator Speed .................................................................................403 29.10 Current Consumption of Peripheral Units ................
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