Datasheet

69
7682C–AUTO–04/08
AT90CAN32/64/128
Figure 9-3. Synchronization when Reading an Externally Applied Pin value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows t
pd,max
and t
pd,min
, a single signal transition on the pin will be delayed
between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in Figure 9-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of
the clock. In this case, the delay t
pd
through the synchronizer is 1 system clock period.
Figure 9-4. Synchronization when Reading a Software Assigned Pin Value