Datasheet

5
7682C–AUTO–04/08
AT90CAN32/64/128
20.1 Overview .........................................................................................................268
20.2 Analog Comparator Register Description .......................................................268
20.3 Analog Comparator Multiplexed Input .............................................................270
21 Analog to Digital Converter - ADC ...................................................... 272
21.1 Features ..........................................................................................................272
21.2 Operation ........................................................................................................273
21.3 Starting a Conversion .....................................................................................274
21.4 Prescaling and Conversion Timing .................................................................275
21.5 Changing Channel or Reference Selection .....................................................278
21.6 ADC Noise Canceler .......................................................................................279
21.7 ADC Conversion Result ..................................................................................283
21.8 ADC Register Description ...............................................................................286
22 JTAG Interface and On-chip Debug System ...................................... 292
22.1 Features ..........................................................................................................292
22.2 Overview .........................................................................................................292
22.3 Test Access Port – TAP ..................................................................................292
22.4 TAP Controller ................................................................................................295
22.5 Using the Boundary-scan Chain .....................................................................296
22.6 Using the On-chip Debug System ...................................................................296
22.7 On-chip Debug Specific JTAG Instructions .....................................................297
22.8 On-chip Debug Related Register in I/O Memory ............................................298
22.9 Using the JTAG Programming Capabilities ....................................................298
22.10 Bibliography ....................................................................................................298
23 Boundary-scan IEEE 1149.1 (JTAG) ................................................... 299
23.1 Features ..........................................................................................................299
23.2 System Overview ............................................................................................299
23.3 Data Registers ................................................................................................299
23.4 Boundary-scan Specific JTAG Instructions .....................................................301
23.5 Boundary-scan Related Register in I/O Memory ............................................303
23.6 Boundary-scan Chain .....................................................................................303
23.7 AT90CAN32/64/128 Boundary-scan Order ....................................................313
23.8 Boundary-scan Description Language Files ...................................................319
24 Boot Loader Support – Read-While-Write Self-Programming ......... 320
24.1 Features ..........................................................................................................320
24.2 Application and Boot Loader Flash Sections ..................................................320