Datasheet

372
7682C–AUTO–04/08
AT90CAN32/64/128
Note: In SPI Programming mode the minimum SCK high/low period is:
- 2 t
CLCL
for f
CK
< 12 MHz
- 3 t
CLCL
for f
CK
>12 MHz
Figure 27-4. SPI Interface Timing Requirements (Master Mode)
Figure 27-5. SPI Interface Timing Requirements (Slave Mode)
13 Setup Slave 10
ns
14 Hold Slave t
ck
15 SCK to out Slave 15
16 SCK to SS high Slave 20
17 SS
high to tri-state Slave 10
18 SS low to SCK Slave 2 • t
ck
Table 27-4. SPI Timing Parameters (Continued)
Description Mode Min. Typ. Max.
MO SI
(Data Output)
SCK
(CPOL = 1)
MISO
(Data Input)
SCK
(CPOL = 0)
SS
MSB LSB
LSBMSB
...
...
6 1
2 2
34 5
8
7
MISO
(Data Output)
SCK
(CPOL = 1)
MO SI
(Data Input)
SCK
(CPOL = 0)
SS
MSB LSB
LSBMSB
...
...
10
11 11
1213 14
17
15
9
X
16
18