Datasheet

297
7682C–AUTO–04/08
AT90CAN32/64/128
• 2 single Program Memory Break Points + 1 Program Memory Break Point with mask (“range
Break Point”).
• 2 single Program Memory Break Points + 1 Data Memory Break Point with mask (“range
Break Point”).
A debugger, like the AVR Studio, may however use one or more of these resources for its inter-
nal purpose, leaving less flexibility to the end-user.
A list of the On-chip Debug specific JTAG instructions is given in
“On-chip Debug Specific JTAG
Instructions” on page 297.
The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the
OCDEN Fuse must be programmed and no Lock bits must be set for the On-chip debug system
to work. As a security feature, the On-chip debug system is disabled when either of the LB1 or
LB2 Lock bits are set. Otherwise, the On-chip debug system would have provided a back-door
into a secured device.
The AVR Studio enables the user to fully control execution of programs on an AVR device with
On-chip Debug capability, AVR In-Circuit Emulator, or the built-in AVR Instruction Set Simulator.
AVR Studio
®
supports source level execution of Assembly programs assembled with Atmel Cor-
poration’s AVR Assembler and C programs compiled with third party vendors’ compilers.
AVR Studio runs under Microsoft
®
Windows
®
95/98/2000/NT/XP.
For a full description of the AVR Studio, please refer to the AVR Studio User Guide. Only high-
lights are presented in this document.
All necessary execution commands are available in AVR Studio, both on source level and on
disassembly level. The user can execute the program, single step through the code either by
tracing into or stepping over functions, step out of functions, place the cursor on a statement and
execute until the statement is reached, stop the execution, and reset the execution target. In
addition, the user can have an unlimited number of code Break Points (using the BREAK
instruction) and up to two data memory Break Points, alternatively combined as a mask (range)
Break Point.
22.7 On-chip Debug Specific JTAG Instructions
The On-chip debug support is considered being private JTAG instructions, and distributed within
ATMEL and to selected third party vendors only. Instruction opcodes are listed for reference.
22.7.1 PRIVATE0 (0x8)
Private JTAG instruction for accessing On-chip debug system.
22.7.2 PRIVATE1 (0x9)
Private JTAG instruction for accessing On-chip debug system.
22.7.3 PRIVATE2 (0xA)
Private JTAG instruction for accessing On-chip debug system.
22.7.4 PRIVATE3 (0xB)
Private JTAG instruction for accessing On-chip debug system.