Datasheet

258
7682C–AUTO–04/08
AT90CAN32/64/128
• Bit 3:1 – PHS12:0: Phase Segment 1
This phase is used to compensate for phase edge errors. This segment may be lengthened by
the re-synchronization jump width.
• Bit 0 – SMP: Sample Point(s)
– 0 - once, at the sample point.
– 1 - three times, the threefold sampling of the bus is the sample point and twice over
a distance of a 1/2 period of the Tscl. The result corresponds to the majority decision
of the three values.
19.10.11 CAN Timer Control Register - CANTCON
• Bit 7:0 – TPRSC7:0: CAN Timer Prescaler
Prescaler for the CAN timer upper counter range 0 to 255. It provides the clock to the CAN timer
if the CAN controller is enabled.
Tclk
CANTIM
= Tclk
IO
x 8 x (CANTCON [7:0] + 1)
19.10.12 CAN Timer Registers - CANTIML and CANTIMH
• Bits 15:0 - CANTIM15:0: CAN Timer Count
CAN timer counter range 0 to 65,535.
19.10.13 CAN TTC Timer Registers - CANTTCL and CANTTCH
• Bits 15:0 - TIMTTC15:0: TTC Timer Count
CAN TTC timer counter range 0 to 65,535.
Tphs1 = Tscl x (PHS1 [2:0] + 1)
Bit 7 6 5 4 3 2 1 0
TPRSC7 TPRSC6 TPRSC5 TPRSC4 TPRSC3 TPRSC2 TRPSC1 TPRSC0 CANTCON
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CANTIM7 CANTIM6 CANTIM5 CANTIM4 CANTIM3 CANTIM2 CANTIM1 CANTIM0 CANTIML
CANTIM15 CANTIM14 CANTIM13 CANTIM12 CANTIM11 CANTIM10 CANTIM9 CANTIM8 CANTIMH
Bit 15 14 13 12 11 10 9 8
Read/Write R R R R R R R R
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
TIMTTC7 TIMTTC6 TIMTTC5 TIMTTC4 TIMTTC3 TIMTTC2 TIMTTC1 TIMTTC0 CANTTCL
TIMTTC15 TIMTTC14 TIMTTC13 TIMTTC12 TIMTTC11 TIMTTC10 TIMTTC9 TIMTTC8 CANTTCH
Bit 15 14 13 12 11 10 9 8
Read/Write R R R R R R R R
Initial Value 0 0 0 0 0 0 0 0