Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 64 (14x14) 8-Bit 16 MHz I/O number 53

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Table Of Contents

Features
1. Description
- 1.1 Comparison Between AT90CAN32, AT90CAN64 and AT90CAN128
- 1.2 Part Description
- 1.3 Disclaimer
- 1.4 Automotive Quality Grade
- 1.5 Block Diagram
- 1.6 Pin Configurations
- 1.7 Pin Descriptions
2. About Code Examples
3. AVR CPU Core
- 3.1 Introduction
- 3.2 Architectural Overview
- 3.3 ALU - Arithmetic Logic Unit
- 3.4 Status Register
- 3.5 General Purpose Register File
  - 3.5.1 The X-register, Y-register, and Z-register
  - 3.5.2 Extended Z-pointer Register for ELPM/SPM - RAMPZ
- 3.6 Stack Pointer
- 3.7 Instruction Execution Timing
- 3.8 Reset and Interrupt Handling
  - 3.8.1 Interrupt Behavior
  - 3.8.2 Interrupt Response Time
4. Memories
- 4.1 In-System Reprogrammable Flash Program Memory
- 4.2 SRAM Data Memory
  - 4.2.1 SRAM Data Access
  - 4.2.2 SRAM Data Access Times
- 4.3 EEPROM Data Memory
- 4.4 I/O Memory
- 4.5 External Memory Interface
- 4.6 General Purpose I/O Registers
5. System Clock
- 5.1 Clock Systems and their Distribution
- 5.2 Clock Sources
- 5.3 Default Clock Source
- 5.4 Crystal Oscillator
- 5.5 Low-frequency Crystal Oscillator
- 5.6 Calibrated Internal RC Oscillator
  - 5.6.1 Oscillator Calibration Register - OSCCAL
- 5.7 External Clock
- 5.8 Clock Output Buffer
- 5.9 Timer/Counter2 Oscillator
- 5.10 System Clock Prescaler
  - 5.10.1 Clock Prescaler Register - CLKPR
6. Power Management and Sleep Modes
- 6.0.1 Sleep Mode Control Register - SMCR
- 6.1 Idle Mode
- 6.2 ADC Noise Reduction Mode
- 6.3 Power-down Mode
- 6.4 Power-save Mode
- 6.5 Standby Mode
- 6.6 Minimizing Power Consumption
7. System Control and Reset
- 7.1 Reset
- 7.2 Internal Voltage Reference
  - 7.2.1 Voltage Reference Enable Signals and Start-up Time
  - 7.2.2 Voltage Reference Characteristics
- 7.3 Watchdog Timer
  - 7.3.1 Watchdog Timer Control Register - WDTCR
- 7.4 Timed Sequences for Changing the Configuration of the Watchdog Timer
  - 7.4.1 Safety Level 1
  - 7.4.2 Safety Level 2
8. Interrupts
- 8.1 Interrupt Vectors in AT90CAN32/64/128
- 8.2 Moving Interrupts Between Application and Boot Space
  - 8.2.1 MCU Control Register - MCUCR
9. I/O-Ports
- 9.1 Introduction
- 9.2 Ports as General Digital I/O
- 9.3 Alternate Port Functions
- 9.4 Register Description for I/O-Ports
10. External Interrupts
- 10.0.1 Asynchronous External Interrupt Control Register A - EICRA
- 10.0.2 Synchronous External Interrupt Control Register B - EICRB
- 10.0.3 External Interrupt Mask Register - EIMSK
- 10.0.4 External Interrupt Flag Register - EIFR
11. Timer/Counter3/1/0 Prescalers
- 11.1 Overview
- 11.2 Timer/Counter0/1/3 Prescalers Register Description
  - 11.2.1 General Timer/Counter Control Register - GTCCR
12. 8-bit Timer/Counter0 with PWM
- 12.1 Features
- 12.2 Overview
  - 12.2.1 Registers
  - 12.2.2 Definitions
- 12.3 Timer/Counter Clock Sources
- 12.4 Counter Unit
- 12.5 Output Compare Unit
- 12.6 Compare Match Output Unit
  - 12.6.1 Compare Output Function
  - 12.6.2 Compare Output Mode and Waveform Generation
- 12.7 Modes of Operation
- 12.8 Timer/Counter Timing Diagrams
- 12.9 8-bit Timer/Counter Register Description
13. 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
- 13.1 Features
- 13.2 Overview
- 13.3 Accessing 16-bit Registers
  - 13.3.1 Code Examples
  - 13.3.2 Reusing the Temporary High Byte Register
- 13.4 Timer/Counter Clock Sources
- 13.5 Counter Unit
- 13.6 Input Capture Unit
- 13.7 Output Compare Units
- 13.8 Compare Match Output Unit
  - 13.8.1 Compare Output Function
  - 13.8.2 Compare Output Mode and Waveform Generation
- 13.9 Modes of Operation
- 13.10 Timer/Counter Timing Diagrams
- 13.11 16-bit Timer/Counter Register Description
14. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
- 14.1 Features
- 14.2 Overview
  - 14.2.1 Definitions
- 14.3 Timer/Counter Clock Sources
- 14.4 Counter Unit
- 14.5 Output Compare Unit
- 14.6 Compare Match Output Unit
  - 14.6.1 Compare Output Function
  - 14.6.2 Compare Output Mode and Waveform Generation
- 14.7 Modes of Operation
- 14.8 Timer/Counter Timing Diagrams
- 14.9 8-bit Timer/Counter Register Description
- 14.10 Asynchronous operation of the Timer/Counter2
- 14.11 Timer/Counter2 Prescaler
  - 14.11.1 General Timer/Counter Control Register - GTCCR
15. Output Compare Modulator - OCM
- 15.1 Overview
- 15.2 Description
  - 15.2.1 Timing Example
  - 15.2.2 Resolution of the PWM Signal
16. Serial Peripheral Interface - SPI
- 16.1 Features
- 16.2 SS Pin Functionality
- 16.3 Data Modes
17. USART (USART0 and USART1)
- 17.1 Features
- 17.2 Overview
- 17.3 Dual USART
- 17.4 Clock Generation
- 17.5 Serial Frame
  - 17.5.1 Frame Formats
  - 17.5.2 Parity Bit Calculation
- 17.6 USART Initialization
- 17.7 Data Transmission - USART Transmitter
- 17.8 Data Reception - USART Receiver
- 17.9 Asynchronous Data Reception
- 17.10 Multi-processor Communication Mode
  - 17.10.1 MPCM Protocol
  - 17.10.2 Using MPCM
- 17.11 USART Register Description
- 17.12 Examples of Baud Rate Setting
18. Two-wire Serial Interface
- 18.1 Features
- 18.2 Two-wire Serial Interface Bus Definition
  - 18.2.1 TWI Terminology
  - 18.2.2 Electrical Interconnection
- 18.3 Data Transfer and Frame Format
- 18.4 Multi-master Bus Systems, Arbitration and Synchronization
- 18.5 Overview of the TWI Module
- 18.6 TWI Register Description
- 18.7 Using the TWI
- 18.8 Transmission Modes
- 18.9 Multi-master Systems and Arbitration
19. Controller Area Network - CAN
- 19.1 Features
- 19.2 CAN Protocol
- 19.3 CAN Controller
- 19.4 CAN Channel
- 19.5 Message Objects
- 19.6 CAN Timer
- 19.7 Error Management
- 19.8 Interrupts
  - 19.8.1 Interrupt organization
  - 19.8.2 Interrupt Behavior
- 19.9 CAN Register Description
- 19.10 General CAN Registers
- 19.11 MOb Registers
- 19.12 Examples of CAN Baud Rate Setting
20. Analog Comparator
- 20.1 Overview
- 20.2 Analog Comparator Register Description
  - 20.2.1 ADC Control and Status Register B - ADCSRB
  - 20.2.2 Analog Comparator Control and Status Register - ACSR
- 20.3 Analog Comparator Multiplexed Input
  - 20.3.1 Digital Input Disable Register 1 - DIDR1
21. Analog to Digital Converter - ADC
- 21.1 Features
- 21.2 Operation
- 21.3 Starting a Conversion
- 21.4 Prescaling and Conversion Timing
  - 21.4.1 Differential Channels
- 21.5 Changing Channel or Reference Selection
  - 21.5.1 ADC Input Channels
  - 21.5.2 ADC Voltage Reference
- 21.6 ADC Noise Canceler
- 21.7 ADC Conversion Result
- 21.8 ADC Register Description
22. JTAG Interface and On-chip Debug System
- 22.1 Features
- 22.2 Overview
- 22.3 Test Access Port - TAP
- 22.4 TAP Controller
- 22.5 Using the Boundary-scan Chain
- 22.6 Using the On-chip Debug System
- 22.7 On-chip Debug Specific JTAG Instructions
- 22.8 On-chip Debug Related Register in I/O Memory
  - 22.8.1 On-chip Debug Register - OCDR
- 22.9 Using the JTAG Programming Capabilities
- 22.10 Bibliography
23. Boundary-scan IEEE 1149.1 (JTAG)
- 23.1 Features
- 23.2 System Overview
- 23.3 Data Registers
- 23.4 Boundary-scan Specific JTAG Instructions
- 23.5 Boundary-scan Related Register in I/O Memory
  - 23.5.1 MCU Control Register - MCUCR
  - 23.5.2 MCU Status Register - MCUSR
- 23.6 Boundary-scan Chain
- 23.7 AT90CAN32/64/128 Boundary-scan Order
- 23.8 Boundary-scan Description Language Files
24. Boot Loader Support - Read-While-Write Self-Programming
- 24.1 Features
- 24.2 Application and Boot Loader Flash Sections
  - 24.2.1 AS - Application Section
  - 24.2.2 BLS - Boot Loader Section
- 24.3 Read-While-Write and No Read-While-Write Flash Sections
  - 24.3.1 RWW - Read-While-Write Section
  - 24.3.2 NRWW - No Read-While-Write Section
- 24.4 Boot Loader Lock Bits
- 24.5 Entering the Boot Loader Program
  - 24.5.1 Store Program Memory Control and Status Register - SPMCSR
- 24.6 Addressing the Flash During Self-Programming
- 24.7 Self-Programming the Flash
25. Memory Programming
- 25.1 Program and Data Memory Lock Bits
- 25.2 Fuse Bits
  - 25.2.1 Latching of Fuses
- 25.3 Signature Bytes
- 25.4 Calibration Byte
- 25.5 Parallel Programming Overview
- 25.6 Parallel Programming
- 25.7 SPI Serial Programming Overview
- 25.8 SPI Serial Programming
  - 25.8.1 Data Polling Flash
  - 25.8.2 Data Polling EEPROM
- 25.9 JTAG Programming Overview
26. Decoupling Capacitors
27. Electrical Characteristics (1)
- 27.1 Absolute Maximum Ratings*
- 27.2 DC Characteristics(1)
- 27.3 External Clock Drive Characteristics
- 27.4 Maximum Speed vs. VCC
- 27.5 Two-wire Serial Interface Characteristics
- 27.6 SPI Timing Characteristics
- 27.7 CAN Physical Layer Characteristics
- 27.8 ADC Characteristics((1)
- 27.9 External Data Memory Characteristics(1)
- 27.10 Parallel Programming Characteristics
28. Register Summary
29. AT90CAN32/64/128 Typical Characteristics
- 29.1 Active Supply Current
- 29.2 Idle Supply Current
- 29.3 Power-down Supply Current
- 29.4 Power-save Supply Current
- 29.5 Pin Pull-up
- 29.6 Pin Driver Strength
- 29.7 Pin Thresholds and Hysteresis
- 29.8 BOD Thresholds and Analog Comparator Offset
- 29.9 Internal Oscillator Speed
- 29.10 Current Consumption of Peripheral Units
- 29.11 Current Consumption in Reset and Reset Pulse Width
- 29.12 Analog To Digital Converter
30. Instruction Set Summary
31. Ordering Information
32. Packaging Information
- 32.1 TQFP64
- 32.2 QFN64
33. Errata
- 33.1 Errata Summary
- 33.2 Errata Description
34. Datasheet Revision History for AT90CAN32/64/128
- 34.1 7682A - 01/07
- 34.2 7682B - 09/07
- 34.3 7682C - 04/08

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7682C–AUTO–04/08

AT90CAN32/64/128

Figure 19-3. CAN Bit Construction

19.2.3.2 Synchronization Segment

The first segment is used to synchronize the various bus nodes.

On transmission, at the start of this segment, the current bit level is output. If there is a bit state

change between the previous bit and the current bit, then the bus state change is expected to

occur within this segment by the receiving nodes.

19.2.3.3 Propagation Time Segment

This segment is used to compensate for signal delays across the network.

This is necessary to compensate for signal propagation delays on the bus line and through the

transceivers of the bus nodes.

19.2.3.4 Phase Segment 1

Phase Segment 1 is used to compensate for edge phase errors.

This segment may be lengthened during re-synchronization.

19.2.3.5 Sample Point

The sample point is the point of time at which the bus level is read and interpreted as the value

of the respective bit. Its location is at the end of Phase Segment 1 (between the two Phase

Segments).

19.2.3.6 Phase Segment 2

This segment is also used to compensate for edge phase errors.

This segment may be shortened during re-synchronization, but the length has to be at least as

long as the Information Processing Time (IPT) and may not be more than the length of Phase

Segment 1.

19.2.3.7 Information Processing Time

It is the time required for the logic to determine the bit level of a sampled bit.

Time Quantum

(producer)

Nominal CAN Bit Time

Segments

(producer)

SYNC_SEG PROP_SEG PHASE_SEG_1 PHASE_SEG_2

propagation

delay

Segments

(consumer)

SYNC_SEG

PROP_SEG PHASE_SEG_1 PHASE_SEG_2

Sample Point

Transmission Point

(producer)

CAN Frame

(producer)