Datasheet
Table Of Contents
- Features
- 1. Description
- 2. About Code Examples
- 3. AVR CPU Core
- 4. Memories
- 4.1 In-System Reprogrammable Flash Program Memory
- 4.2 SRAM Data Memory
- 4.3 EEPROM Data Memory
- 4.4 I/O Memory
- 4.5 External Memory Interface
- 4.5.1 Overview
- 4.5.2 Using the External Memory Interface
- 4.5.3 Address Latch Requirements
- 4.5.4 Pull-up and Bus-keeper
- 4.5.5 Timing
- 4.5.6 External Memory Control Register A - XMCRA
- 4.5.7 External Memory Control Register B - XMCRB
- 4.5.8 Using all Locations of External Memory Smaller than 64 KB
- 4.5.9 Using all 64KB Locations of External Memory
- 4.6 General Purpose I/O Registers
- 5. System Clock
- 6. Power Management and Sleep Modes
- 7. System Control and Reset
- 8. Interrupts
- 9. I/O-Ports
- 9.1 Introduction
- 9.2 Ports as General Digital I/O
- 9.3 Alternate Port Functions
- 9.4 Register Description for I/O-Ports
- 9.4.1 Port A Data Register - PORTA
- 9.4.2 Port A Data Direction Register - DDRA
- 9.4.3 Port A Input Pins Address - PINA
- 9.4.4 Port B Data Register - PORTB
- 9.4.5 Port B Data Direction Register - DDRB
- 9.4.6 Port B Input Pins Address - PINB
- 9.4.7 Port C Data Register - PORTC
- 9.4.8 Port C Data Direction Register - DDRC
- 9.4.9 Port C Input Pins Address - PINC
- 9.4.10 Port D Data Register - PORTD
- 9.4.11 Port D Data Direction Register - DDRD
- 9.4.12 Port D Input Pins Address - PIND
- 9.4.13 Port E Data Register - PORTE
- 9.4.14 Port E Data Direction Register - DDRE
- 9.4.15 Port E Input Pins Address - PINE
- 9.4.16 Port F Data Register - PORTF
- 9.4.17 Port F Data Direction Register - DDRF
- 9.4.18 Port F Input Pins Address - PINF
- 9.4.19 Port G Data Register - PORTG
- 9.4.20 Port G Data Direction Register - DDRG
- 9.4.21 Port G Input Pins Address - PING
- 10. External Interrupts
- 11. Timer/Counter3/1/0 Prescalers
- 12. 8-bit Timer/Counter0 with PWM
- 13. 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
- 13.1 Features
- 13.2 Overview
- 13.3 Accessing 16-bit Registers
- 13.4 Timer/Counter Clock Sources
- 13.5 Counter Unit
- 13.6 Input Capture Unit
- 13.7 Output Compare Units
- 13.8 Compare Match Output Unit
- 13.9 Modes of Operation
- 13.10 Timer/Counter Timing Diagrams
- 13.11 16-bit Timer/Counter Register Description
- 13.11.1 Timer/Counter1 Control Register A - TCCR1A
- 13.11.2 Timer/Counter3 Control Register A - TCCR3A
- 13.11.3 Timer/Counter1 Control Register B - TCCR1B
- 13.11.4 Timer/Counter3 Control Register B - TCCR3B
- 13.11.5 Timer/Counter1 Control Register C - TCCR1C
- 13.11.6 Timer/Counter3 Control Register C - TCCR3C
- 13.11.7 Timer/Counter1 - TCNT1H and TCNT1L
- 13.11.8 Timer/Counter3 - TCNT3H and TCNT3L
- 13.11.9 Output Compare Register A - OCR1AH and OCR1AL
- 13.11.10 Output Compare Register B - OCR1BH and OCR1BL
- 13.11.11 Output Compare Register C - OCR1CH and OCR1CL
- 13.11.12 Output Compare Register A - OCR3AH and OCR3AL
- 13.11.13 Output Compare Register B - OCR3BH and OCR3BL
- 13.11.14 Output Compare Register C - OCR3CH and OCR3CL
- 13.11.15 Input Capture Register - ICR1H and ICR1L
- 13.11.16 Input Capture Register - ICR3H and ICR3L
- 13.11.17 Timer/Counter1 Interrupt Mask Register - TIMSK1
- 13.11.18 Timer/Counter3 Interrupt Mask Register - TIMSK3
- 13.11.19 Timer/Counter1 Interrupt Flag Register - TIFR1
- 13.11.20 Timer/Counter3 Interrupt Flag Register - TIFR3
- 14. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
- 14.1 Features
- 14.2 Overview
- 14.3 Timer/Counter Clock Sources
- 14.4 Counter Unit
- 14.5 Output Compare Unit
- 14.6 Compare Match Output Unit
- 14.7 Modes of Operation
- 14.8 Timer/Counter Timing Diagrams
- 14.9 8-bit Timer/Counter Register Description
- 14.10 Asynchronous operation of the Timer/Counter2
- 14.11 Timer/Counter2 Prescaler
- 15. Output Compare Modulator - OCM
- 16. Serial Peripheral Interface - SPI
- 17. USART (USART0 and USART1)
- 17.1 Features
- 17.2 Overview
- 17.3 Dual USART
- 17.4 Clock Generation
- 17.5 Serial Frame
- 17.6 USART Initialization
- 17.7 Data Transmission - USART Transmitter
- 17.8 Data Reception - USART Receiver
- 17.9 Asynchronous Data Reception
- 17.10 Multi-processor Communication Mode
- 17.11 USART Register Description
- 17.11.1 USART0 I/O Data Register - UDR0
- 17.11.2 USART1 I/O Data Register - UDR1
- 17.11.3 USART0 Control and Status Register A - UCSR0A
- 17.11.4 USART1 Control and Status Register A - UCSR1A
- 17.11.5 USART0 Control and Status Register B - UCSR0B
- 17.11.6 USART1 Control and Status Register B - UCSR1B
- 17.11.7 USART0 Control and Status Register C - UCSR0C
- 17.11.8 USART1 Control and Status Register C - UCSR1C
- 17.11.9 USART0 Baud Rate Registers - UBRR0L and UBRR0H
- 17.11.10 USART1 Baud Rate Registers - UBRR1L and UBRR1H
- 17.12 Examples of Baud Rate Setting
- 18. Two-wire Serial Interface
- 19. Controller Area Network - CAN
- 19.1 Features
- 19.2 CAN Protocol
- 19.2.1 Principles
- 19.2.2 Message Formats
- 19.2.3 CAN Bit Timing
- 19.2.3.1 Bit Construction
- 19.2.3.2 Synchronization Segment
- 19.2.3.3 Propagation Time Segment
- 19.2.3.4 Phase Segment 1
- 19.2.3.5 Sample Point
- 19.2.3.6 Phase Segment 2
- 19.2.3.7 Information Processing Time
- 19.2.3.8 Bit Lengthening
- 19.2.3.9 Bit Shortening
- 19.2.3.10 Synchronization Jump Width
- 19.2.3.11 Programming the Sample Point
- 19.2.3.12 Synchronization
- 19.2.4 Arbitration
- 19.2.5 Errors
- 19.3 CAN Controller
- 19.4 CAN Channel
- 19.5 Message Objects
- 19.6 CAN Timer
- 19.7 Error Management
- 19.8 Interrupts
- 19.9 CAN Register Description
- 19.10 General CAN Registers
- 19.10.1 CAN General Control Register - CANGCON
- 19.10.2 CAN General Status Register - CANGSTA
- 19.10.3 CAN General Interrupt Register - CANGIT
- 19.10.4 CAN General Interrupt Enable Register - CANGIE
- 19.10.5 CAN Enable MOb Registers - CANEN2 and CANEN1
- 19.10.6 CAN Enable Interrupt MOb Registers - CANIE2 and CANIE1
- 19.10.7 CAN Status Interrupt MOb Registers - CANSIT2 and CANSIT1
- 19.10.8 CAN Bit Timing Register 1 - CANBT1
- 19.10.9 CAN Bit Timing Register 2 - CANBT2
- 19.10.10 CAN Bit Timing Register 3 - CANBT3
- 19.10.11 CAN Timer Control Register - CANTCON
- 19.10.12 CAN Timer Registers - CANTIML and CANTIMH
- 19.10.13 CAN TTC Timer Registers - CANTTCL and CANTTCH
- 19.10.14 CAN Transmit Error Counter Register - CANTEC
- 19.10.15 CAN Receive Error Counter Register - CANREC
- 19.10.16 CAN Highest Priority MOb Register - CANHPMOB
- 19.10.17 CAN Page MOb Register - CANPAGE
- 19.11 MOb Registers
- 19.11.1 CAN MOb Status Register - CANSTMOB
- 19.11.2 CAN MOb Control and DLC Register - CANCDMOB
- 19.11.3 CAN Identifier Tag Registers - CANIDT1, CANIDT2, CANIDT3, and CANIDT4
- 19.11.4 CAN Identifier Mask Registers - CANIDM1, CANIDM2, CANIDM3, and CANIDM4
- 19.11.5 CAN Time Stamp Registers - CANSTML and CANSTMH
- 19.11.6 CAN Data Message Register - CANMSG
- 19.12 Examples of CAN Baud Rate Setting
- 20. Analog Comparator
- 21. Analog to Digital Converter - ADC
- 22. JTAG Interface and On-chip Debug System
- 23. Boundary-scan IEEE 1149.1 (JTAG)
- 24. Boot Loader Support - Read-While-Write Self-Programming
- 24.1 Features
- 24.2 Application and Boot Loader Flash Sections
- 24.3 Read-While-Write and No Read-While-Write Flash Sections
- 24.4 Boot Loader Lock Bits
- 24.5 Entering the Boot Loader Program
- 24.6 Addressing the Flash During Self-Programming
- 24.7 Self-Programming the Flash
- 24.7.1 Performing Page Erase by SPM
- 24.7.2 Filling the Temporary Buffer (Page Loading)
- 24.7.3 Performing a Page Write
- 24.7.4 Using the SPM Interrupt
- 24.7.5 Consideration While Updating BLS
- 24.7.6 Prevent Reading the RWW Section During Self-Programming
- 24.7.7 Setting the Boot Loader Lock Bits by SPM
- 24.7.8 EEPROM Write Prevents Writing to SPMCSR
- 24.7.9 Reading the Fuse and Lock Bits from Software
- 24.7.10 Preventing Flash Corruption
- 24.7.11 Programming Time for Flash when Using SPM
- 24.7.12 Simple Assembly Code Example for a Boot Loader
- 24.7.13 Boot Loader Parameters
- 25. Memory Programming
- 25.1 Program and Data Memory Lock Bits
- 25.2 Fuse Bits
- 25.3 Signature Bytes
- 25.4 Calibration Byte
- 25.5 Parallel Programming Overview
- 25.6 Parallel Programming
- 25.6.1 Enter Programming Mode
- 25.6.2 Considerations for Efficient Programming
- 25.6.3 Chip Erase
- 25.6.4 Programming the Flash
- 25.6.5 Programming the EEPROM
- 25.6.6 Reading the Flash
- 25.6.7 Reading the EEPROM
- 25.6.8 Programming the Fuse Low Bits
- 25.6.9 Programming the Fuse High Bits
- 25.6.10 Programming the Extended Fuse Bits
- 25.6.11 Programming the Lock Bits
- 25.6.12 Reading the Fuse and Lock Bits
- 25.6.13 Reading the Signature Bytes
- 25.6.14 Reading the Calibration Byte
- 25.7 SPI Serial Programming Overview
- 25.8 SPI Serial Programming
- 25.9 JTAG Programming Overview
- 25.9.1 Programming Specific JTAG Instructions
- 25.9.2 Data Registers
- 25.9.3 Programming Algorithm
- 25.9.3.1 Entering Programming Mode
- 25.9.3.2 Leaving Programming Mode
- 25.9.3.3 Performing Chip Erase
- 25.9.3.4 Programming the Flash
- 25.9.3.5 Reading the Flash
- 25.9.3.6 Programming the EEPROM
- 25.9.3.7 Reading the EEPROM
- 25.9.3.8 Programming the Fuses
- 25.9.3.9 Programming the Lock Bits
- 25.9.3.10 Reading the Fuses and Lock Bits
- 25.9.3.11 Reading the Signature Bytes
- 25.9.3.12 Reading the Calibration Byte
- 26. Decoupling Capacitors
- 27. Electrical Characteristics (1)
- 27.1 Absolute Maximum Ratings*
- 27.2 DC Characteristics(1)
- 27.3 External Clock Drive Characteristics
- 27.4 Maximum Speed vs. VCC
- 27.5 Two-wire Serial Interface Characteristics
- 27.6 SPI Timing Characteristics
- 27.7 CAN Physical Layer Characteristics
- 27.8 ADC Characteristics((1)
- 27.9 External Data Memory Characteristics(1)
- 27.10 Parallel Programming Characteristics
- 28. Register Summary
- 29. AT90CAN32/64/128 Typical Characteristics
- 29.1 Active Supply Current
- 29.2 Idle Supply Current
- 29.3 Power-down Supply Current
- 29.4 Power-save Supply Current
- 29.5 Pin Pull-up
- 29.6 Pin Driver Strength
- 29.7 Pin Thresholds and Hysteresis
- 29.8 BOD Thresholds and Analog Comparator Offset
- 29.9 Internal Oscillator Speed
- 29.10 Current Consumption of Peripheral Units
- 29.11 Current Consumption in Reset and Reset Pulse Width
- 29.12 Analog To Digital Converter
- 30. Instruction Set Summary
- 31. Ordering Information
- 32. Packaging Information
- 33. Errata
- 34. Datasheet Revision History for AT90CAN32/64/128
235
7682C–AUTO–04/08
AT90CAN32/64/128
19.2.2.2 CAN Extended Frame
Figure 19-2. CAN Extended Frames
A message in the CAN extended frame format is likely the same as a message in CAN standard
frame format. The difference is the length of the identifier used. The identifier is made up of the
existing 11-bit identifier (base identifier) and an 18-bit extension (identifier extension). The dis-
tinction between CAN standard frame format and CAN extended frame format is made by using
the IDE bit which is transmitted as dominant in case of a frame in CAN standard frame format,
and transmitted as recessive in the other case.
19.2.2.3 Format Co-existence
As the two formats have to co-exist on one bus, it is laid down which message has higher priority
on the bus in the case of bus access collision with different formats and the same identifier /
base identifier: The message in CAN standard frame format always has priority over the mes-
sage in extended format.
There are three different types of CAN modules available:
– 2.0A - Considers 29 bit ID as an error
– 2.0B Passive - Ignores 29 bit ID messages
– 2.0B Active - Handles both 11 and 29 bit ID Messages
19.2.3 CAN Bit Timing
To ensure correct sampling up to the last bit, a CAN node needs to re-synchronize throughout
the entire frame. This is done at the beginning of each message with the falling edge SOF and
on each recessive to dominant edge.
19.2.3.1 Bit Construction
One CAN bit time is specified as four non-overlapping time segments. Each segment is con-
structed from an integer multiple of the Time Quantum. The Time Quantum or TQ is the smallest
discrete timing resolution used by a CAN node.
11-bit base identifier
IDT28..18
Interframe
Space
CRC
del.
ACK
del.
15-bit CRC
0 - 8 bytes
SOF
SOF
SRR IDE ACK
7 bits
Intermission
3 bits
Bus Idle Bus Idle
(Indefini
Arbitration
Field
Arbitration
Field
Data
Field
Data Frame
Control
Field
Control
Field
End of
Frame
CRC
Field
ACK
Field
Interframe
Space
11-bit base identifier
IDT28..18
18-bit identifier extension
ID17..0
18-bit identifier extension
ID17..0
Interframe
Space
4-bit DLC
DLC4..0
CRC
del.
ACK
del.
15-bit CRC
SOF
SOF
SRR IDE r0
4-bit DLC
DLC4..0
RTR
RTR
r0r1
r1 ACK
7 bits
Intermission
3 bits
Bus Idle Bus Idle
(Indefinite)
Remote Frame
End of
Frame
CRC
Field
ACK
Field
Interframe
Space