Datasheet

71
4235K–8051–05/08
AT89C51RD2/ED2
Reset Value = 00X0 XXXXb
Not Bit addressable
16.3.5.3 Serial Peripheral DATa Register (SPDAT)
The Serial Peripheral Data Register (Table 16-5) is a read/write buffer for the receive data regis-
ter. A write to SPDAT places data directly into the shift register. No transmit buffer is available in
this model.
A Read of the SPDAT returns the value located in the receive buffer and not the content of the
shift register.
Table 16-5. SPDAT Register
SPDAT - Serial Peripheral Data Register (0C5H)
Reset Value = Indeterminate
R7:R0: Receive data bits
SPCON, SPSTA and SPDAT registers may be read and written at any time while there is no on-
going exchange. However, special care should be taken when writing to them while a transmis-
sion is on-going:
• Do not change SPR2, SPR1 and SPR0
• Do not change CPHA and CPOL
• Do not change MSTR
• Clearing SPEN would immediately disable the peripheral
• Writing to the SPDAT will cause an overflow.
5 SSERR
Synchronous Serial Slave Error Flag
Set by hardware when SS is de-asserted before the end of a received data.
Cleared by disabling the SPI (clearing SPEN bit in SPCON).
4 MODF
Mode Fault
Cleared by hardware to indicate that the SS pin is at appropriate logic level, or has been
approved by a clearing sequence.
Set by hardware to indicate that the SS pin is at inappropriate logic level.
3 -
Reserved
The value read from this bit is indeterminate. Do not set this bit
2 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Bit Number
Bit
Mnemonic Description
7 6 5 4 3 2 1 0
R7 R6 R5 R4 R3 R2 R1 R0