Datasheet

65
4235K–8051–05/08
AT89C51RD2/ED2
16.3 Functional Description
Figure 16-2 shows a detailed structure of the SPI Module.
Figure 16-2. SPI Module Block Diagram
16.3.1 Operating Modes
The Serial Peripheral Interface can be configured in one of the two modes: Master mode or
Slave mode. The configuration and initialization of the SPI Module is made through one register:
• The Serial Peripheral Control register (SPCON)
Once the SPI is configured, the data exchange is made using:
• SPCON
• The Serial Peripheral STAtus register (SPSTA)
• The Serial Peripheral DATa register (SPDAT)
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the
two serial data lines (MOSI and MISO). A Slave Select line (SS) allows individual selection of a
Slave SPI device; Slave devices that are not selected do not interfere with SPI bus activities.
When the Master device transmits data to the Slave device via the MOSI line, the Slave device
responds by sending data to the Master device via the MISO line. This implies full-duplex trans-
mission with both data out and data in synchronized with the same clock (Figure 16-3).
Shift Register
01
234567
Internal Bus
Pin
Control
Logic
MISO
MOSI
SCK
M
S
Clock
Logic
Clock
Divider
Clock
Select
/4
/64
/128
SPI Interrupt Request
8-bit bus
1-bit signal
SS
FCLK PERIPH
/32
/8
/16
Receive Data Register
SPDAT
SPI
Control
SPSTA
CPHA
SPR0
SPR1
CPOLMSTRSSDISSPEN
SPR2
SPCON
WCOL MODFSPIF
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