Datasheet

26
4235K–8051–05/08
AT89C51RD2/ED2
10. Reset
10.1 Introduction
The reset sources are: Power Management, Hardware Watchdog, PCA Watchdog and Reset
input.
Figure 10-1. Reset schematic
10.2 Reset Input
The Reset input can be used to force a reset pulse longer than the internal reset controlled by
the Power Monitor. RST input has a pull-down resistor allowing power-on reset by simply con-
necting an external capacitor to V
CC
as shown in Figure 10-2. Resistor value and input
characteristics are discussed in the Section “DC Characteristics” of the AT89C51RD2/ED2
datasheet.
Figure 10-2. Reset Circuitry and Power-On Reset
10.3 Reset Output
Reset output can be generated by two sources:
• Internal POR/PFD
• Hardware watchdog timer
As detailed in Section “Hardware Watchdog Timer”, page 84, the WDT generates a 96-clock
period pulse on the RST pin.
In order to properly propagate this pulse to the rest of the application in case of external capaci-
tor or power-supply supervisor circuit, a 1 kΩ resistor must be added as shown Figure 10-3.
Power
Monitor
Hardware
Watchdog
PCA
Watchdog
RST
Internal Reset
RST
R
RST
VSS
To internal reset
RST
VDD
+
b. Power-on Reseta. RST input circuitry