Datasheet

18
4235K–8051–05/08
AT89C51RD2/ED2
Figure 7-1. Clock Generation Diagram
Figure 7-2. Mode Switching Waveforms
The X2 bit in the CKCON0 register (see Table 7-1) allows a switch from 12 clock periods per
instruction to 6 clock periods and vice versa. At reset, the speed is set according to X2 bit of
Hardware Security Byte (HSB). By default, Standard mode is active. Setting the X2 bit activates
the X2 feature (X2 mode).
The T0X2, T1X2, T2X2, UartX2, PcaX2, and WdX2 bits in the CKCON0 register (Table 7-1) and
SPIX2 bit in the CKCON1 register (see Table 7-2) allows a switch from standard peripheral
speed (12 clock periods per peripheral clock cycle) to fast peripheral speed (6 clock periods per
peripheral clock cycle). These bits are active only in X2 mode.
Table 7-1. CKCON0 Register
CKCON0 - Clock Control Register (8Fh)
XTAL1
2
CKCON0
X2
8-bit Prescaler
F
OSC
FXTAL
0
1
XTAL1:2
F
CLK CPU
F
CLK PERIPH
CKRL
XTAL1:2
XTAL1
CPU Clock
X2 Bit
X2 ModeSTD Mode STD Mode
F
OSC
7 6 5 4 3 2 1 0
- WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2
Bit
Number
Bit
Mnemonic Description
7 Reserved The values for this bit are indeterminite. Do not set this bit.
6 WDX2
Watchdog Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no
effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.