Datasheet

15
4235K–8051–05/08
AT89C51RD2/ED2
6. Oscillator
To optimize the power consumption and execution time needed for a specific task, an internal
prescaler feature has been implemented between the oscillator and the CPU and peripherals.
6.1 Registers
Table 6-1. CKRL Register
CKRL – Clock Reload Register (97h)
Reset Value = 1111 1111b
Not bit addressable
Table 6-2. PCON Register
PCON – Power Control Register (87h)
Reset Value = 00X1 0000b Not bit addressable
7 6 5 4 3 2 1 0
CKRL7 CKRL6 CKRL5 CKRL4 CKRL3 CKRL2 CKRL1 CKRL0
Bit Number Mnemonic Description
7:0 CKRL
Clock Reload Register
Prescaler value
7 6 5 4 3 2 1 0
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit Number Bit Mnemonic Description
7 SMOD1
Serial Port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6 SMOD0
Serial Port Mode bit 0
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
5 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 POF
Power-off Flag
Cleared by software to recognize the next reset type.
Set by hardware when V
CC
rises from 0 to its nominal voltage. Can also be
set by software.
3 GF1
General-purpose Flag
Cleared by software for general-purpose usage.
Set by software for general-purpose usage.
2 GF0
General-purpose Flag
Cleared by software for general-purpose usage.
Set by software for general-purpose usage.
1 PD
Power-down Mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0 IDL
Idle Mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.