Datasheet

4235K–8051–05/08

AT89C51RD2/ED2

Reset Value = XXXX XXX0b

Not bit addressable

2 - Reserved

1 - Reserved

0 SPIX2

SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit

has no effect).

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Bit

Number

Bit

Mnemonic Description