Datasheet

116
4235K–8051–05/08
AT89C51RD2/ED2
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total I
OL
for all output pins: 71 mA
If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
7. The maximum dV/dt value specifies the maximum Vcc drop to issure no internal POR/PFD reset.
Figure 25-1. I
CC
Test Condition, Active Mode
Figure 25-2. I
CC
Test Condition, Idle Mode
Figure 25-3. I
CC
Test Condition, Power-down Mode
EA
V
CC
V
CC
I
CC
(NC)
CLOCK
SIGNAL
V
CC
All other pins are disconnected.
RST
XTAL2
XTAL1
V
SS
V
CC
P0
RST
EA
XTAL2
XTAL1
V
SS
V
CC
V
CC
I
CC
(NC)
P0
V
CC
All other pins are disconnected.
CLOCK
SIGNAL
RST
EA
XTAL2
XTAL1
V
SS
V
CC
V
CC
I
CC
(NC)
P0
V
CC
All other pins are disconnected.