Features • 80C52 Compatible • • • • • • • • • • • • • • • • • • • • • • • – 8051 Instruction Compatible – Six 8-bit I/O Ports (64 Pins or 68 Pins Versions) – Four 8-bit I/O Ports (44 Pins Version) – Three 16-bit Timer/Counters – 256 Bytes Scratch Pad RAM – 9 Interrupt Sources with 4 Priority Levels Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply ISP (In-System Programming) Using Standard VCC Power Supply 2048 Bytes Boot ROM Contains Low Level Flash Programming Routines and a Defa
1. Description AT89C51RD2/ED2 is high performance CMOS Flash version of the 80C51 CMOS single chip 8bit microcontroller. It contains a 64-Kbyte Flash memory block for code and for data. The 64-Kbytes Flash memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard VCC pin.
AT89C51RD2/ED2 2. Block Diagram (2) (2) Flash 64K x 8 RAM 256x8 XRAM PCA 1792 x 8 Keyboard T2 T2EX (1) (1) (1) EUART XTALA1 PCA ECI VSS TxD VCC Block Diagram RxD Figure 2-1.
3.
AT89C51RD2/ED2 Table 3-3.
Table 3-5. Timer SFRs Mnemonic Add Name TL2 CCh Timer/Counter 2 Low Byte Table 3-6.
AT89C51RD2/ED2 Table 3-9. Keyboard Interface SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 KBLS 9Ch Keyboard Level Selector KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0 KBE 9Dh Keyboard Input Enable KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0 KBF 9Eh Keyboard Flag Register KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0 5 4 3 2 1 0 EEE EEBUSY Table 3-10.
Table 3-11.
AT89C51RD2/ED2 4. Pin Configurations P0.2/AD2 P0.3/AD3 P0.1/AD1 P0.0/AD0 VCC P1.0/T2 NIC* P1.1/T2EX/SS P1.2/ECI P1.3/CEX0 Pin Configurations P1.4/CEX1 Figure 4-1. 6 5 4 3 2 1 44 43 42 41 40 P1.5/CEX2/MISO 39 38 P0.4/AD4 P1.6/CEX3/SCK 7 8 P1.7/CEx4/MOSI 9 37 P0.6/AD6 RST 10 36 P0.7/AD7 P3.0/RxD 11 12 13 35 34 33 EA NIC* 14 15 32 31 PSEN 16 30 P2.6/A14 17 29 P2.5/A13 NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 AT89C51RD2/ED2 PLCC44 P0.5/AD5 ALE/PROG P2.7/A15 P0.
NIC P2.7/A15 P2.6/A14 P5.2 P5.1 P2.5/A13 PSEN NIC ALE EA P0.4/AD4 P5.4 P5.3 P0.5/AD5 P0.6/AD6 NIC P0.7/AD7 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 AT89C51ED2 PLCC68 P5.0 P2.4/A12 P2.3/A11 P4.7 P2.2/A10 P2.1/A9 P2.0/A8 P4.6 NIC VSS P4.5 XTAL1 XTAL2 P3.7/RD P4.4 P3.6/WR P4.3 P1.5/CEX2/MISO27 P1.6/CEX3/SCK28 P1.7/CEX4/MOSI29 RST 30 NIC 31 NIC 32 NIC 33 P3.0/RxD 34 NIC 35 NIC 36 NIC 37 NIC 38 P3.1/TxD 39 P3.2/INT0 40 P3.3/INT1 41 P3.4/T0 42 P3.
AT89C51RD2/ED2 Table 4-1. Pin Description Pin Number Type Mnemonic PLCC44 VQFP44 PLCC68 VQFP64 Name and Function VSS 22 16 51 40 I Ground: 0V reference VCC 44 38 17 8 I Power Supply: This is the power supply voltage for normal, idle and power-down operation P0.0 - P0.7 43 - 36 37 - 30 15, 14, 12, 11, 9,6, 5, 3 6, 5, 3, 2, 64, 61,60,59 P1.0 - P1.
Table 4-1. Pin Description (Continued) Pin Number Type Mnemonic PLCC44 VQFP44 9 3 PLCC68 VQFP64 29 20 Name and Function I/O P1.7: Input/Output: I/O CEX4: Capture/Compare External I/O for PCA module 4 I/O MOSI: SPI Master Output Slave Input line When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in slave mode, MOSI receives data from the master controller.
AT89C51RD2/ED2 Table 4-1. Pin Description (Continued) Pin Number Type Mnemonic PLCC44 VQFP44 PLCC68 VQFP64 Name and Function Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory.
5. Port Types AT89C51RD2/ED2 I/O ports (P1, P2, P3, P4, P5) implement the quasi-bidirectional output that is common on the 80C51 and most of its derivatives. This output type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin is pulled low, it is driven strongly and able to sink a fairly large current.
AT89C51RD2/ED2 6. Oscillator To optimize the power consumption and execution time needed for a specific task, an internal prescaler feature has been implemented between the oscillator and the CPU and peripherals. 6.1 Registers Table 6-1. CKRL Register CKRL – Clock Reload Register (97h) 7 6 5 4 3 2 1 0 CKRL7 CKRL6 CKRL5 CKRL4 CKRL3 CKRL2 CKRL1 CKRL0 Bit Number Mnemonic 7:0 CKRL Description Clock Reload Register Prescaler value Reset Value = 1111 1111b Not bit addressable Table 6-2.
6.2 Functional Block Diagram Figure 6-1. Functional Oscillator Block Diagram Reload Reset CKRL FOSC Xtal1 Osc 1 Xtal2 :2 8-bit Prescaler-Divider 0 1 CLK Periph X2 0 CKCON0 CLK CPU Peripheral Clock CPU Clock Idle CKRL = 0xFF? 6.2.
AT89C51RD2/ED2 7. Enhanced Features In comparison to the original 80C52, the AT89C51RD2/ED2 implements some new features, which are: • X2 option • Dual Data Pointer • Extended RAM • Programmable Counter Array (PCA) • Hardware Watchdog • SPI interface • 4-level interrupt priority system • Power-off flag • ONCE mode • ALE disabling • Some enhanced features are also located in the UART and the Timer 2 7.1 X2 Feature The AT89C51RD2/ED2 core needs only 6 clock periods per machine cycle.
Figure 7-1. Clock Generation Diagram CKRL 2 XTAL1 FOSC XTAL1:2 0 FXTAL FCLK CPU FCLK PERIPH 8-bit Prescaler 1 X2 CKCON0 Figure 7-2. Mode Switching Waveforms XTAL1 XTAL1:2 X2 Bit FOSC CPU Clock STD Mode X2 Mode STD Mode The X2 bit in the CKCON0 register (see Table 7-1) allows a switch from 12 clock periods per instruction to 6 clock periods and vice versa. At reset, the speed is set according to X2 bit of Hardware Security Byte (HSB). By default, Standard mode is active.
AT89C51RD2/ED2 Bit Bit Number Mnemonic Description Programmable Counter Array Clock 5 PCAX2 (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Enhanced UART Clock (Mode 0 and 2) 4 SIX2 (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect).
Bit Bit Number Mnemonic 2 - Reserved 1 - Reserved 0 SPIX2 Description SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
AT89C51RD2/ED2 8. Dual Data Pointer Register (DPTR) The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1.0 (see Table 8-1) that allows the program code to switch between them (Refer to Figure 8-1). Figure 8-1.
Reset Value = XXXX XX0X0b Not bit addressable Note: 1. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.
AT89C51RD2/ED2 9. Expanded RAM (XRAM) The AT89C51RD2/ED2 provides additional on-chip random access memory (RAM) space for increased data parameter handling and high level language usage. AT89C51RD2/ED2 device haS expanded RAM in external data space configurable up to 1792 bytes (see Table 9-1). The AT89C51RD2/ED2 internal data memory is mapped into four separate segments. The four segments are: 1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly addressable. 2.
part of the available XRAM as explained in Table 9-1. This can be useful if external peripherals are mapped at addresses already used by the internal XRAM. • With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. An access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD).
AT89C51RD2/ED2 Bit Bit Number Mnemonic Description EXTRAM bit Cleared to access internal XRAM using movx @ Ri/ @ DPTR. 1 EXTRAM Set to access external memory. Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), default setting, XRAM selected. 0 AO ALE Output bit Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC instruction is used.
10. Reset 10.1 Introduction The reset sources are: Power Management, Hardware Watchdog, PCA Watchdog and Reset input. Figure 10-1. Reset schematic Power Monitor Hardware Watchdog Internal Reset PCA Watchdog RST 10.2 Reset Input The Reset input can be used to force a reset pulse longer than the internal reset controlled by the Power Monitor. RST input has a pull-down resistor allowing power-on reset by simply connecting an external capacitor to V CC as shown in Figure 10-2.
AT89C51RD2/ED2 Figure 10-3.
11. Power Monitor The POR/PFD function monitors the internal power-supply of the CPU core memories and the peripherals, and if needed, suspends their activity when the internal power supply falls below a safety threshold. This is achieved by applying an internal reset to them. By generating the Reset the Power Monitor insures a correct start up when AT89C51RD2/ED2 is powered up. 11.
AT89C51RD2/ED2 Figure 11-2. Power Fail Detect Vcc VPFDP VPFDM t Reset Vcc When the power is applied, the Power Monitor immediately asserts a reset. Once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL clock input. The internal reset will remain asserted until the Xtal1 levels are above and below VIH and VIL. Further more. An internal counter will count 1024 clock periods before the reset is de-asserted.
12. Timer 2 The Timer 2 in the AT89C51RD2/ED2 is the standard C52 Timer 2. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 are cascaded. It is controlled by T2CON (Table 12-1) and T2MOD (Table 12-2) registers. Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects FOSC/12 (timer operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to increment by the selected input.
AT89C51RD2/ED2 Figure 12-1. Auto-reload Mode Up/Down Counter (DCEN = 1) FCLK PERIPH :6 0 1 T2 C/T2 TR2 T2CON T2CON (DOWN COUNTING RELOAD VALUE) T2EX: If DCEN = 1, 1 = UP FFh FFh If DCEN = 1, 0 = DOWN (8-bit) (8-bit) If DCEN = 0, up counting TOGGLE T2CON EXF2 TL2 TH2 (8-bit) (8-bit) TF2 TIMER 2 INTERRUPT T2CON RCAP2L (8-bit) RCAP2H (8-bit) (UP COUNTING RELOAD VALUE) 12.
It is possible to use Timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers. Figure 12-2. Clock-out Mode C/T2 = 0 :6 FCLK PERIPH TR2 T2CON TL2 (8-bit) TH2 (8-bit) OVERFLOW RCAP2L RCAP2H (8-bit) (8-bit) Toggle T2 Q D T2OE T2MOD T2EX T2CON EXEN2 T2CON 12.3 TIMER 2 INTERRUPT EXF2 Registers Table 12-1.
AT89C51RD2/ED2 Bit Bit Number Mnemonic 7 TF2 Description Timer 2 overflow Flag Must be cleared by software. Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0. 6 EXF2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2 = 1. When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2 interrupt is enabled. Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1).
Table 12-2. T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h) 7 6 5 4 3 2 1 0 - - - - - - T2OE DCEN Bit Bit Number Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
AT89C51RD2/ED2 13. Programmable Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules.
• The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows. Figure 13-1. PCA Timer/Counter To PCA Modules FCLK PERIPH/6 Overflow FCLK PERIPH/2 CH T0 OVF IT CL 16 Bit Up Counter P1.
AT89C51RD2/ED2 Table 13-1. CMOD Register CMOD - PCA Counter Mode Register (D9h) 7 6 5 4 3 2 1 0 CIDL WDTE - - - CPS1 CPS0 ECF Bit Bit Number Mnemonic 7 CIDL Description Counter Idle Control Cleared to program the PCA Counter to continue functioning during idle Mode. Set to program PCA to be gated off during idle. Watchdog Timer Enable 6 WDTE Cleared to disable Watchdog Timer function on PCA Module 4. Set to enable Watchdog Timer function on PCA Module 4.
Table 13-2. CCON Register CCON - PCA Counter Control Register (D8h) 7 6 5 4 3 2 1 0 CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 Bit Bit Number Mnemonic Description PCA Counter Overflow flag 7 CF Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software. PCA Counter Run control bit 6 CR Must be cleared by software to turn the PCA counter off.
AT89C51RD2/ED2 Figure 13-2. PCA Interrupt System CF CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8 PCA Timer/Counter Module 0 Module 1 To Interrupt Priority Decoder Module 2 Module 3 Module 4 CMOD.0 ECF ECCFn CCAPMn.0 IEN0.6 EC IEN0.7 EA PCA Modules: each one of the five compare/capture modules has six possible functions.
Table 13-3 shows the CCAPMn settings for the various PCA functions. Table 13-3.
AT89C51RD2/ED2 Table 13-4. PCA Module Modes (CCAPMn Registers) ECOMn CAPPn CAPNn MATn TOGn PWMm ECCFn Module Function 0 0 0 0 0 0 0 No Operation X 1 0 0 0 0 X 16-bit capture by a positive-edge trigger on CEXn X 0 1 0 0 0 X 16-bit capture by a negative trigger on CEXn X 1 1 0 0 0 X 16-bit capture by a transition on CEXn 1 0 0 1 0 0 X 16-bit Software Timer/Compare mode.
Table 13-6.
AT89C51RD2/ED2 13.1 PCA Capture Mode To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and CCAPnH).
Figure 13-4. PCA Compare Mode and PCA Watchdog Timer CCON CF Write to CCAPnL CR CCF4 CCF3 CCF2 CCF1 CCF0 0xD8 Reset PCA IT Write to CCAPnH 1 CCAPnH 0 CCAPnL Enable Match 16 bit comparator CH RESET * CL PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CIDL WDTE CPS1 CPS0 ECF CCAPMn, n = 0 to 4 0xDA to 0xDE CMOD 0xD9 Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit.
AT89C51RD2/ED2 Figure 13-5. PCA High Speed Output Mode CCON CF CR CCF4 CCF3 CCF2 CCF1 CCF0 0xD8 Write to CCA PnL Reset PCA IT Write to CCAPnH 1 CCAPnH 0 CCAPnL Enable 16 bit comparator CH Match CL CEXn PCA counter/timer ECO Mn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n = 0 to 4 0xDA to 0xDE Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen.
Figure 13-6. PCA PWM Mode CCAPnH Overflow CCAPnL “0” CEXn Enable 8-bit Comparator “1” CL PCA Counter/Timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n= 0 to 4 0xDA to 0xDE 13.5 PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge.
AT89C51RD2/ED2 The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option.
14. Serial I/O Port The serial I/O port in the AT89C51RD2/ED2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates Serial I/O port includes the following enhancements: • Framing error detection • Automatic address recognition 14.
AT89C51RD2/ED2 Figure 14-3. UART Timings in Modes 2 and 3 RXD D0 Start bit D1 D2 D3 D4 Data byte D5 D6 D7 D8 Ninth Stop bit bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 14.2 Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set).
Slave C:SADDR1111 0010b SADEN1111 1101b Given1111 00X1b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1.To communicate with slave A only, the master must send an address where bit 0 is clear (e. g. 1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.
AT89C51RD2/ED2 14.3 Registers Table 14-1. SADEN Register SADEN - Slave Address Mask Register (B9h) 7 6 5 4 3 2 1 0 4 3 2 1 0 Reset Value = 0000 0000b Not bit addressable Table 14-2. SADDR Register SADDR - Slave Address Register (A9h) 7 6 5 Reset Value = 0000 0000b Not bit addressable 14.4 Baud Rate Selection for UART for Mode 1 and 3 The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers. Figure 14-4.
Table 14-3. 14.4.
AT89C51RD2/ED2 Table 14-4. SCON Register SCON - Serial Control Register (98h) 7 6 5 4 3 2 1 0 FE/SM0 SM1 SM2 REN TB8 RB8 TI RI Bit Bit Number Mnemonic Description Framing Error bit (SMOD0=1) FE Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit. 7 SM0 Serial port Mode bit 0 Refer to SM1 for serial port mode selection.
Table 14-5. Example of Computed Value When X2=1, SMOD1=1, SPD=1 Baud Rates FOSC = 16. 384 MHz FOSC = 24MHz BRL Error (%) BRL Error (%) 115200 247 1.23 243 0.16 57600 238 1.23 230 0.16 38400 229 1.23 217 0.16 28800 220 1.23 204 0.16 19200 203 0.63 178 0.16 9600 149 0.31 100 0.16 4800 43 1.23 - - Table 14-6. Example of Computed Value When X2=0, SMOD1=0, SPD=0 Baud Rates FOSC = 16. 384 MHz FOSC = 24MHz BRL Error (%) BRL Error (%) 4800 247 1.23 243 0.
AT89C51RD2/ED2 Table 14-9. SBUF Register SBUF - Serial Buffer Register for UART (99h) 7 6 5 4 3 2 1 0 Reset Value = XXXX XXXXb Table 14-10.
Table 14-11. T2CON Register T2CON - Timer 2 Control Register (C8h) 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Bit Bit Number Mnemonic 7 TF2 Description Timer 2 overflow Flag Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0. 6 EXF2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.
AT89C51RD2/ED2 Table 14-12. PCON Register PCON - Power Control Register (87h) 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Bit Number Mnemonic 7 SMOD1 6 SMOD0 5 - 4 POF Power-Off Flag Cleared to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. 3 GF1 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage.
Table 14-13. BDRCON Register BDRCON - Baud Rate Control Register (9Bh) 7 6 5 4 3 2 1 0 - - - BRR TBCK RBCK SPD SRC Bit Number Bit Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit 6 - Reserved The value read from this bit is indeterminate. Do not set this bit 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 BRR Baud Rate Run Control bit Cleared to stop the internal Baud Rate Generator.
AT89C51RD2/ED2 15. Keyboard Interface The AT89C51RD2/ED2 implements a keyboard interface allowing the connection of a 8 x n matrix keyboard. It is based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1 and allow to exit from idle and power-down modes.
15.1 Registers Table 15-1. KBF Register KBF-Keyboard Flag Register (9Eh) 7 6 5 4 3 2 1 0 KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0 Bit Number Bit Mnemonic Description 7 KBF7 Keyboard line 7 flag Set by hardware when the Port line 7 detects a programmed level. It generates a Keyboard interrupt request if the KBKBIE.7 bit in KBIE register is set. Must be cleared by software. 6 KBF6 Keyboard line 6 flag Set by hardware when the Port line 6 detects a programmed level.
AT89C51RD2/ED2 Table 15-2. KBE Register KBE-Keyboard Input Enable Register (9Dh) 7 6 5 4 3 2 1 0 KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0 Bit Number Bit Mnemonic Description 7 KBE7 Keyboard line 7 Enable bit Cleared to enable standard I/O pin. Set to enable KBF.7 bit in KBF register to generate an interrupt request. 6 KBE6 Keyboard line 6 Enable bit Cleared to enable standard I/O pin. Set to enable KBF.6 bit in KBF register to generate an interrupt request.
Table 15-3. KBLS Register KBLS-Keyboard Level Selector Register (9Ch) 7 6 5 4 3 2 1 0 KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0 Bit Number Bit Mnemonic Description 7 KBLS7 Keyboard line 7 Level Selection bit Cleared to enable a low level detection on Port line 7. Set to enable a high level detection on Port line 7. 6 KBLS6 Keyboard line 6 Level Selection bit Cleared to enable a low level detection on Port line 6. Set to enable a high level detection on Port line 6.
AT89C51RD2/ED2 16. Serial Port Interface (SPI) The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. 16.
16.2.3 SPI Serial Clock (SCK) This signal is used to synchronize the data movement both in and out of the devices through their MOSI and MISO lines. It is driven by the Master for eight clock cycles which allows to exchange one Byte on the serial lines. 16.2.4 Slave Select (SS) Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any message for a Slave. It is obvious that only one Master (SS high level) can drive the network.
AT89C51RD2/ED2 16.3 Functional Description Figure 16-2 shows a detailed structure of the SPI Module. Figure 16-2. SPI Module Block Diagram Internal Bus SPDAT Shift Register FCLK PERIPH Clock Divider /4 /8 /16 /32 /64 /128 7 6 5 4 3 2 1 0 Receive Data Register Pin Control Logic Clock Logic MOSI MISO M S Clock Select SCK SS SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0 SPCON SPI Control SPI Interrupt Request 8-bit bus 1-bit signal SPSTA SPIF WCOL 16.3.
Figure 16-3. Full-Duplex Master-Slave Interconnection 8-bit Shift register SPI Clock Generator MISO MISO MOSI MOSI SCK SS Master MCU 8-bit Shift register SCK VDD SS VSS Slave MCU 16.3.1.1 Master Mode The SPI operates in Master mode when the Master bit, MSTR (1), in the SPCON register is set. Only one Master SPI device can initiate transmissions. Software begins the transmission from a Master SPI Module by writing to the Serial Peripheral Data Register (SPDAT).
AT89C51RD2/ED2 Figure 16-4. Data Transmission Format (CPHA = 0) SCK Cycle Number 1 2 3 4 5 6 7 8 MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB bit6 bit5 bit4 bit3 bit2 bit1 LSB SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) MSB SS (to Slave) Capture Point Figure 16-5.
16.3.3.1 Mode Fault (MODF) Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the actual mode of the device. MODF is set to warn that there may be a multimaster conflict for system control. In this case, the SPI system is affected in the following ways: • An SPI receiver/error CPU interrupt request is generated • The SPEN bit in SPCON is cleared.
AT89C51RD2/ED2 Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been completed. SPIF bit generates transmitter CPU interrupt requests. Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is inconsistent with the mode of the SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt requests. When SSDIS is set, no MODF interrupt request is generated. Figure 16-7 gives a logical view of the above statements. Figure 16-7.
Bit Number Bit Mnemonic 4 MSTR Description Serial Peripheral Master Cleared to configure the SPI as a Slave. Set to configure the SPI as a Master. Clock Polarity 3 CPOL Cleared to have the SCK set to ’0’ in idle state. Set to have the SCK set to ’1’ in idle low. Clock Phase 2 Cleared to have the data sampled when the SCK leaves the idle state (see CPOL). CPHA Set to have the data sampled when the SCK returns to idle state (see CPOL).
AT89C51RD2/ED2 Bit Number Bit Mnemonic 5 SSERR Description Synchronous Serial Slave Error Flag Set by hardware when SS is de-asserted before the end of a received data. Cleared by disabling the SPI (clearing SPEN bit in SPCON). Mode Fault 4 MODF Cleared by hardware to indicate that the SS pin is at appropriate logic level, or has been approved by a clearing sequence. Set by hardware to indicate that the SS pin is at inappropriate logic level.
17. Interrupt System The AT89C51RD2/ED2 has a total of 9 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard interrupt and the PCA global interrupt. These interrupts are shown in Figure 17-1. Figure 17-1.
AT89C51RD2/ED2 17.1 Registers The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located at address 004BH and Keyboard interrupt vector is located at address 003BH. All other vectors addresses are the same as standard C52 devices. Table 17-1. Priority Level Bit Values IPH.x IPL.
Table 17-3. IENO Register IEN0 - Interrupt Enable Register (A8h) 7 6 5 4 3 2 1 0 EA EC ET2 ES ET1 EX1 ET0 EX0 Bit Bit Number Mnemonic 7 EA 6 EC Description Enable All interrupt bit Cleared to disable all interrupts. Set to enable all interrupts. PCA interrupt enable bit Cleared to disable. Set to enable. 5 ET2 Timer 2 overflow interrupt Enable bit Cleared to disable timer 2 overflow interrupt. Set to enable timer 2 overflow interrupt.
AT89C51RD2/ED2 Table 17-4. IPL0 Register IPL0 - Interrupt Priority Register (B8h) 7 6 5 4 3 2 1 0 - PPCL PT2L PSL PT1L PX1L PT0L PX0L Bit Bit Number Mnemonic 7 - 6 PPCL PCA interrupt Priority bit Refer to PPCH for priority level. 5 PT2L Timer 2 overflow interrupt Priority bit Refer to PT2H for priority level. 4 PSL Serial port Priority bit Refer to PSH for priority level. 3 PT1L Timer 1 overflow interrupt Priority bit Refer to PT1H for priority level.
Table 17-5. IPH0 Register IPH0 - Interrupt Priority High Register (B7h) 7 6 5 4 3 2 1 0 - PPCH PT2H PSH PT1H PX1H PT0H PX0H Bit Number Mnemonic 7 - 6 5 4 3 2 1 0 Bit Description Reserved The value read from this bit is indeterminate. Do not set this bit. PPCH PCA interrupt Priority high bit.
AT89C51RD2/ED2 Table 17-6. IEN1 Register IEN1 - Interrupt Enable Register (B1h) 7 6 5 4 3 2 1 0 - - - - - ESPI - KBD Bit Bit Number Mnemonic 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved 2 ESPI Description SPI interrupt Enable bit Cleared to disable SPI interrupt. Set to enable SPI interrupt. Reserved 1 0 KBD Keyboard interrupt Enable bit Cleared to disable keyboard interrupt. Set to enable keyboard interrupt.
Table 17-7. IPL1 Register IPL1 - Interrupt Priority Register (B2h) 7 6 5 4 3 2 1 0 - - - - - SPIL TWIL KBDL Bit Bit Number Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
AT89C51RD2/ED2 Table 17-8. IPH1 Register IPH1 - Interrupt Priority High Register (B3h) 7 6 5 4 3 2 1 0 - - - - - SPIH - KBDH Bit Number Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
18. Power Management 18.1 Introduction Two power reduction modes are implemented in the AT89C51RD2/ED2. The Idle mode and the Power-Down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 mode detailed in Section “Enhanced Features”, page 17. 18.2 Idle Mode Idle mode is a power reduction mode that reduces the power consumption. In this mode, program execution halts.
AT89C51RD2/ED2 18.3 Power-Down Mode The Power-Down mode places the AT89C51RD2/ED2 in a very low power state. Power-Down mode stops the oscillator, freezes all clock at known states. The CPU status prior to entering Power-Down mode is preserved, i.e., the program counter, program status word register retain their data for the duration of Power-Down mode. In addition, the SFR and RAM contents are preserved. The status of the Port pins during Power-Down mode is detailed in Table 18-1.
continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the AT89C51RD2/ED2 and vectors the CPU to address 0000h. 3. Generate an enabled external Keyboard interrupt (same behavior as external interrupt). Note: During the time that execution resumes, the internal RAM cannot be accessed; however, it is possible for the Port pins to be accessed.
AT89C51RD2/ED2 18.4 Registers Table 18-2. PCON Register PCON (S87:h) Power configuration Register 7 6 5 4 3 2 1 0 - - - - GF1 GF0 PD IDL Bit Number Bit Mnemonic Description 7-4 - 3 GF1 General Purpose flag 1 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode. 2 GF0 General Purpose flag 0 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode.
19. Hardware Watchdog Timer The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the Watchdog Timer ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H.
AT89C51RD2/ED2 Table 19-2. WDTPRG Register WDTPRG - Watchdog Timer Out Register (0A7h) 7 6 5 4 3 2 1 0 - - - - - S2 S1 S0 Bit Bit Number Mnemonic 7 - 6 - 5 - 4 - 3 - 2 S2 WDT Time-out select bit 2 1 S1 WDT Time-out select bit 1 0 S0 WDT Time-out select bit 0 Description Reserved The value read from this bit is undetermined. Do not try to set this bit. S2 0 0 0 0 1 1 1 1 S1 S0Selected Time-out 00 (214 - 1) machine cycles, 16.
20. ONCE® Mode (ON- Chip Emulation) The ONCE mode facilitates testing and debugging of systems using AT89C51RD2/ED2 without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the AT89C51RD2/ED2; the following sequence must be exercised: • Pull ALE low while the device is in reset (RST high) and PSEN is high. • Hold ALE low as RST is deactivated. While the AT89C51RD2/ED2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit.
AT89C51RD2/ED2 21. Power-off Flag The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced by VCC switch-on. A warm start reset occurs while VCC is still applied to the device and could be generated for example by an exit from power-down. The power-off flag (POF) is located in PCON register (Table 21-1). POF is set by hardware when VCC rises from 0 to its nominal voltage.
22. Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches.
AT89C51RD2/ED2 23. EEPROM Data Memory This feature is available only for the AT89C51ED2 device. The 2K bytes on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/ERAM memory space and is selected by setting control bits in the EECON register. A read or write access to the EEPROM memory is done with a MOVX instruction. 23.1 Write Data Data is written by byte to the EEPROM memory block as for an external RAM memory.
Figure 23-1. Recommended EEPROM Data Write Sequence EEPROM Data Write Sequence EEBusy Cleared? Save & Disable IT EA= 0 EEPROM Data Mapping EECON = 02h (EEE=1) Data Write DPTR= Address ACC= Data Exec: MOVX @DPTR, A EEPROM Mapping EECON = 00h (EEE=0) Restore IT Last Byte to Load? 23.2 Read Data The following procedure is used to read the data stored in the EEPROM memory: • Check EEBUSY flag • If the user application interrupts routines use XRAM memory space: Save and disable interrupts.
AT89C51RD2/ED2 Figure 23-2. Recommended EEPROM Data Read Sequence EEPROM Data Read Sequence EEBusy Cleared? Save & Disable IT EA= 0 EEPROM Data Mapping EECON = 02h (EEE=1) Data Read DPTR= Address ACC= Data Exec: MOVX A, @DPTR Last Byte to Read? EEPROM Data Mapping EECON = 00h (EEE = 0 Restore IT 23.3 Registers Table 23-1.
Bit Number 1 Bit Mnemonic EEE Description Enable EEPROM Space bit Set to map the EEPROM space during MOVX instructions (Write or Read to the EEPROM. Clear to map the XRAM space during MOVX. 0 EEBUSY Programming Busy flag Set by hardware when programming is in progress. Cleared by hardware when programming is done. Can not be set or cleared by software.
AT89C51RD2/ED2 24. Flash/EEPROM Memory The Flash memory increases EEPROM and ROM functionality with in-circuit electrical erasure and programming. It contains 64K bytes of program memory organized respectively in 512 pages of 128 bytes. This memory is both parallel and serial In-System Programmable (ISP). ISP allows devices to alter their own program memory in the actual end product under software control. A default serial loader (bootloader) program allows ISP of the Flash.
24.3 Flash Registers and Memory Map The AT89C51RD2/ED2 Flash memory uses several registers for its management: • Hardware register can only be accessed through the parallel programming modes which are handled by the parallel programmer. • Software registers are in a special page of the Flash memory which can be accessed through the API or with the parallel programming modes. This page, called "Extra Flash Memory", is not in the internal Flash program memory addressing space. 24.3.
AT89C51RD2/ED2 Table 24-2. Program Lock Bits Program Lock Bits Security Level LB0 LB1 LB2 1 U U U No program lock features enabled. U MOVC instruction executed from external program memory is disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further parallel programming of the on chip code memory is disabled. 2 P U Protection Description ISP and software programming with API are still allowed.
Mnemonic Definition Default value Description BSB Boot Status Byte 0FFh SSB Software Security Byte FFh Copy of the Manufacturer Code 58h Atmel Copy of the Device ID #1: Family Code D7h C51 X2, Electrically Erasable Copy of the Device ID #2: Memories Size and Type ECh AT89C51RD2/ED2 64KB Copy of the Device ID #3: Name and Revision EFh AT89C51RD2/ED2 64KB, Revision 0 After programming the part by ISP, the BSB must be cleared (00h) in order to allow the application to boot at 0000h.
AT89C51RD2/ED2 Table 24-5. User Memory Lock Bits of the SSB Program Lock Bits Security Level LB0 LB1 1 1 1 No program lock features enabled. 2 0 1 ISP programming of the Flash is disabled. 3 X 0 Same as 2, also verify through ISP programming interface is disabled. Note: 24.4 Protection Description X: Do not care WARNING: Security level 2 and 3 should only be programmed after Flash verification.
Figure 24-2. Diagram Context Description Access Via Specific Protocol Bootloader Flash Memory Access From User Application 24.6.
AT89C51RD2/ED2 24.6.3 Functional Description Figure 24-3. Bootloader Functional Description External Host with Specific Protocol Communication User Application User Call Management (API) ISP Communication Management Flash Memory Management Flash Memory On the above diagram, the on-chip bootloader processes are: • ISP Communication Management The purpose of this process is to manage the communication and its protocol between the onchip bootloader and a external device.
24.6.4 Bootloader Functionality The bootloader can be activated by two means: Hardware conditions or regular boot process. The Hardware conditions (EA = 1, PSEN = 0) during the Reset# falling edge force the on-chip bootloader execution. This allows an application to be built that will normally execute the end user’s code but can be manually forced into default ISP operation.
AT89C51RD2/ED2 24.6.5 Boot Process Figure 24-5.
24.7 24.7.1 ISP Protocol Description Physical Layer The UART used to transmit information has the following configuration: • Character: 8-bit data • Parity: none • Stop: 2 bits • Flow control: none • Baudrate: autobaud is performed by the bootloader to compute the baudrate chosen by the host. 24.7.2 Frame Description The Serial Protocol is based on the Intel Hex-type records. Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below. Figure 24-6.
AT89C51RD2/ED2 24.8 24.8.1 Functional Description Software Security Bits (SSB) The SSB protects any Flash access from ISP command. The command "Program Software Security Bit" can only write a higher priority level. There are three levels of security: • level 0: NO_SECURITY (FFh) This is the default level. From level 0, one can write level 1 or level 2. • level 1: WRITE_SECURITY (FEh) For this level it is impossible to write in the Flash memory, BSB and SBV. The Bootloader returns ’P’ on write access.
• SBV = FCh • SSB = FFh The Full Chip Erase does not affect the bootloader. 24.8.3 24.9 24.9.1 Checksum Error When a checksum error is detected, send ‘X’ followed with CR&LF. Flow Description Overview An initialization step must be performed after each Reset. After microcontroller reset, the bootloader waits for an autobaud sequence (see section ‘Autobaud Performances’). When the communication is initialized, the protocol depends on the record type requested by the host.
AT89C51RD2/ED2 Table 24-8. Autobaud Performances (Continued) Frequency (MHz) Baudrate (kHz) 24.9.4 1.8432 2 2.4576 3 3.6864 4 5 6 7.3728 4800 OK - OK OK OK OK OK OK OK 9600 OK - OK OK OK OK OK OK OK 19200 OK - OK OK OK - - OK OK 38400 - - OK OK - OK OK OK 57600 - - - - OK - - - OK 115200 - - - - - - - - OK Frequency (MHz) Baudrate (kHz) 8 10 11.0592 12 14.746 16 20 24 26.
24.9.5 Write/Program Commands Description This flow is common to the following frames: • Flash/EEPROM Programming Data Frame • EOF or Atmel Frame (only Programming Atmel Frame) • Config Byte Programming Data Frame • Baud Rate Frame Figure 24-9.
AT89C51RD2/ED2 24.9.5.1 Example Programming Data (write 55h at address 0010h in the Flash) HOST : 01 0010 00 55 9A BOOTLOADER : 01 0010 00 55 9A . CR LF Programming Atmel function (write SSB to level 2) HOST : 02 0000 03 05 01 F5 BOOTLOADER : 02 0000 03 05 01 F5. CR LF Writing Frame (write BSB to 55h) 24.9.6 HOST : 03 0000 03 06 00 55 9F BOOTLOADER : 03 0000 03 06 00 55 9F . CR LF Blank Check Command Description Figure 24-10.
24.9.6.1 Example Blank Check ok HOST : 05 0000 04 0000 7FFF 01 78 BOOTLOADER : 05 0000 04 0000 7FFF 01 78 .
AT89C51RD2/ED2 24.9.7 Display Data Description Figure 24-11.
• Reading Frame • EOF Frame/ Atmel Frame (only reading Atmel Frame) Figure 24-12. Read Flow Bootloader Host Read Command Send Read Command Wait Read Command OR Checksum error ’X’ & CR & LF Wait Checksum Error Send Checksum error COMMAND ABORTED RD_WR_SECURITY OR ’L’ & CR & LF Wait Security Error Send Security error COMMAND ABORTED Read Value ’value’ & ’.’ & CR & LF Wait Value of Data Send Data Read COMMAND FINISHED 24.9.8.
AT89C51RD2/ED2 Table 24-9.
24.10 API Call Description The IAP allows to reprogram a microcontroller on-chip Flash memory without removing it from the system and while the embedded application is running. The user application can call some Application Programming Interface (API) routines allowing IAP. These API are executed by the bootloader. To call the corresponding API, the user must use a set of Flash_api routines which can be linked with the application.
AT89C51RD2/ED2 Table 24-10.
25. Electrical Characteristics 25.1 Absolute Maximum Ratings Note: I = industrial ........................................................-40°C to 85°C Storage Temperature .................................... -65°C to + 150°C Voltage on VCC to VSS ......................................-0.5V to + 6.5V VVoltage on Any Pin to VSS .......................-0.5V to VCC + 0.5V Power Dissipation ........................................................... 1 W(2) 25.
AT89C51RD2/ED2 TA = -40°C to +85°C; VSS = 0V; VCC =2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution) VCC =4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only) (Continued) Symbol Parameter Min Typ Max Unit Test Conditions VCC = 5V ± 10% VOH1 Output High Voltage, port 0, ALE, PSEN VCC - 0.3 V IOH = -200 µA VCC - 0.7 V IOH = -3.2 mA VCC - 1.5 V IOH = -7.0 mA 0.9 VCC V IOH = -10 µA VCC = 2.7V to 5.
Port 0: 26 mA Ports 1, 2 and 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 7. The maximum dV/dt value specifies the maximum Vcc drop to issure no internal POR/PFD reset. Figure 25-1. ICC Test Condition, Active Mode VCC ICC VCC VCC P0 VCC RST EA XTAL2 XTAL1 (NC) CLOCK SIGNAL VSS All other pins are disconnected. Figure 25-2.
AT89C51RD2/ED2 Figure 25-4. Clock Signal Waveform for ICC Tests in Active and Idle Modes VCC-0.5V 0.45V TCLCH TCHCL TCLCH = TCHCL = 5ns. 25.3 25.3.1 0.7VCC 0.2VCC-0.1 AC Parameters Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for.
25.3.2 External Program Memory Characteristics Table 25-1. Symbol Description Symbol T Table 25-2.
AT89C51RD2/ED2 Table 25-3. 25.3.3 AC Parameters for a Variable Clock Symbol Type Standard Clock X2 Clock X parameter for -M range Units TLHLL Min 2T-x T-x 15 ns TAVLL Min T-x 0.5 T - x 20 ns TLLAX Min T-x 0.5 T - x 20 ns TLLIV Max 4T-x 2T-x 35 ns TLLPL Min T-x 0.5 T - x 15 ns TPLPH Min 3T-x 1.5 T - x 25 ns TPLIV Max 3T-x 1.5 T - x 45 ns TPXIX Min x x 0 ns TPXIZ Max T-x 0.5 T - x 15 ns TAVIV Max 5T-x 2.
Table 25-4. Symbol Description Symbol Table 25-5.
AT89C51RD2/ED2 Table 25-6. 25.3.5 AC Parameters for a Variable Clock Symbol Type Standard Clock X2 Clock X parameter for -M range Units TRLRH Min 6T-x 3T-x 25 ns TWLWH Min 6T-x 3T-x 25 ns TRLDV Max 5T-x 2.5 T - x 30 ns TRHDX Min x x 0 ns TRHDZ Max 2T-x T-x 25 ns TLLDV Max 8T-x 4T -x 45 ns TAVDV Max 9T-x 4.5 T - x 65 ns TLLWL Min 3T-x 1.5 T - x 30 ns TLLWL Max 3T+x 1.5 T + x 30 ns TAVWL Min 4T-x 2T-x 30 ns TQVWX Min T-x 0.
25.3.6 External Data Memory Read Cycle TWHLH TLLDV ALE PSEN TLLWL TRLRH RD TRHDZ TAVDV TLLAX PORT 0 TRHDX A0-A7 DATA IN TRLAZ TAVWL PORT 2 25.3.7 ADDRESS OR SFR-P2 ADDRESS A8-A15 OR SFR P2 Serial Port Timing - Shift Register Mode Table 25-7. Symbol Description Symbol Table 25-8.
AT89C51RD2/ED2 Table 25-9. 25.3.
25.3.11 Float Waveforms FLOAT VOH - 0.1V VOL + 0.1V VLOAD VLOAD + 0.1V VLOAD - 0.1V For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH ≥ ± 20 mA. 25.3.12 124 Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.
AT89C51RD2/ED2 Figure 25-5.
26. Ordering Information Table 26-1. Possible Order Entries Part Number Data EEPROM Supply Voltage Temperature Range Package Packing Product Marking PLCC44 Stick AT89C51RD2-UM VQFP44 Tray AT89C51RD2-UM VQFP64 Tray AT89C51RD2-UM PLCC68 Stick AT89C51RD2-UM PLCC44 Stick AT89C51ED2-UM VQFP44 Tray AT89C51ED2-UM AT89C51ED2- SMSUM PLCC68 Stick AT89C51ED2-UM AT89C51ED2-RDTUM VQFP64 Tray AT89C51ED2-UM AT89C51RD2-SLSUM AT89C51RD2-RLTUM No AT89C51RD2-RDTUM(1) AT89C51RD2-SMSUM(1) 2.
AT89C51RD2/ED2 27. Packaging Information 27.
STANDARD NOTES FOR PLCC 1/ CONTROLLING DIMENSIONS : INCHES 2/ DIMENSIONING AND TOLERANCING PER ANSI Y 14.5M - 1982. 3/ "D" AND "E1" DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSIONS. MOLD FLASH OR PROTUSIONS SHALL NOT EXCEED 0.20 mm (.008 INCH) PER SIDE.
AT89C51RD2/ED2 27.
STANDARD NOTES FOR PQFP/ VQFP / TQFP / DQFP 1/ CONTROLLING DIMENSIONS : INCHES 2/ ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y 14.5M 1982. 3/ "D1 AND E1" DIMENSIONS DO NOT INCLUDE MOLD PROTUSIONS. MOLD PROTUSIONS SHALL NOT EXCEED 0.25 mm (0.010 INCH). THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM PACKAGE BODY SIZE BY AS MUCH AS 0.15 mm. 4/ DATUM PLANE "H" LOCATED AT MOLD PARTING LINE AND COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT BOTTOM OF PARTING LINE.
AT89C51RD2/ED2 27.
27.
AT89C51RD2/ED2 28. Document Revision History 28.1 Changes from 4235A -04/03 to 4135B - 06/03 1. VIH min changed from 0.2 VCC + 1.1 to 0.2 VCC + 0.9. 2. Added POR/PFD and reset specific sections. 3. Added DIL40 package. 4. Added Flash write programming time specification. 28.2 Changes from 4235B -06/03 to 4235C - 08/03 1. Changed maximum frequency to 60 MHz in X1 mode and 30 MHz in X2 mode for Vcc = 4.5V to 5.5V and internal code execution. 2. Added PDIL40 Packaging for AT89C51ED2. 28.
AT89C51RD2/ED2 Features .................................................................................................... 1 1 Description ............................................................................................... 2 2 Block Diagram .......................................................................................... 3 3 SFR Mapping ............................................................................................ 4 4 Pin Configurations ...........................
14 Serial I/O Port ......................................................................................... 48 14.1 Framing Error Detection ..................................................................................48 14.2 Automatic Address Recognition ......................................................................49 14.3 Registers .........................................................................................................51 14.
AT89C51RD2/ED2 24.3 Flash Registers and Memory Map ...................................................................94 24.4 Flash Memory Status....................................................................................... 97 24.5 Memory Organization ......................................................................................97 24.6 Bootloader Architecture ...................................................................................97 24.7 ISP Protocol Description ........
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