Datasheet

25
AT89C51RB2/RC2
4180E–8051–10/06
Registers Table 19. AUXR Register
AUXR - Auxiliary Register (8Eh)
Reset Value = XX0X 00’HSB. XRAM’0b (see Table 65)
Not bit addressable
76543210
DPU - M0 - XRS1 XRS0 EXTRAM AO
Bit
Number
Bit
Mnemonic Description
7DPU
Disable Weak Pull-up
Cleared to activate the permanent weak pull up when latch data is logical 1
Set to disactive the weak pull-up (reduce power consumption)
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5M0
Pulse Length
Cleared to stretch MOVX control: the RD
and the WR pulse length is 6 clock
periods (default).
Set to stretch MOVX control: the RD
and the WR pulse length is 30 clock
periods.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3XRS1XRAM Size
XRS1
XRS0 XRAM size
0 0 256 Bytes (default)
0 1 512 Bytes
1 0 768 Bytes
1 1 1024 Bytes
2XRS0
1 EXTRAM
EXTRAM Bit
Cleared to access internal XRAM using movx @ Ri/ @ DPTR.
Set to access external memory.
Programmed by hardware after Power-up regarding Hardware Security Byte
(HSB), default setting, XRAM selected.
0AO
ALE Output Bit
Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if
X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC
instruction is used.