Datasheet

21
AT89C51RB2/RC2
4180E–8051–10/06
Table 17. AUXR1 register
AUXR1- Auxiliary Register 1(0A2h)
Reset Value = XXXX XX0X0b
Not bit addressable
Note: 1. Bit 2 stuck at 0; this allows using INC AUXR1 to toggle DPS without changing GF3.
ASSEMBLY LANGUAGE
; Block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a Byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the Byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
76543210
- - ENBOOT - GF3 0 - DPS
Bit
Number
Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 ENBOOT
Enable Boot Flash
Cleared to disable boot ROM.
Set to map the boot ROM between F800h - 0FFFFh.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3GF3This bit is a general-purpose user flag.
(1)
20Always Cleared
1-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0DPS
Data Pointer Selection
Cleared to select DPTR0.
Set to select DPTR1.