Datasheet
Table Of Contents
- Features
- Description
- Block Diagram
- SFR Mapping
- Pin Configurations
- Oscillators
- Enhanced Features
- Dual Data Pointer Register DPTR
- Expanded RAM (XRAM)
- Reset
- Power Monitor
- Timer 2
- Programmable Counter Array PCA
- Serial I/O Port
- Interrupt System
- Power Management
- Keyboard Interface
- 2-wire Interface (TWI)
- Serial Port Interface (SPI)
- Hardware Watchdog Timer
- ONCE(TM) Mode (ON Chip Emulation)
- Power-off Flag
- EEPROM Data Memory
- Reduced EMI Mode
- Flash Memory
- Electrical Characteristics
- Absolute Maximum Ratings
- DC Parameters
- AC Parameters
- Explanation of the AC Symbols
- External Program Memory Characteristics
- External Program Memory Read Cycle
- External Data Memory Characteristics
- External Data Memory Write Cycle
- External Data Memory Read Cycle
- Serial Port Timing - Shift Register Mode
- Shift Register Timing Waveforms
- External Clock Drive Waveforms
- AC Testing Input/Output Waveforms
- Float Waveforms
- Clock Waveforms
- Ordering Information
- Packaging Information
- Table of Contents
95
AT89C51ID2
4289C–8051–11/05
Registers Table 71. SSCON Register
SSCON - Synchronous Serial Control register (93h)
76543210
CR2 SSIE STA STO SI AA CR1 CR0
Bit
Number
Bit
Mnemonic Description
7CR2
Control Rate bit 2
See Table 65.
6SSIE
Synchronous Serial Interface Enable bit
Clear to disable the TWI module.
Set to enable the TWI module.
5STA
Start flag
Set to send a START condition on the bus.
4ST0
Stop flag
Set to send a STOP condition on the bus.
3SI
Synchronous Serial Interrupt flag
Set by hardware when a serial interrupt is requested.
Must be cleared by software to acknowledge interrupt.
2AA
Assert Acknowledge flag
Clear in master and slave receiver modes, to force a not acknowledge (high level
on SDA).
Clear to disable SLA or GCA recognition.
Set to recognise SLA or GCA (if GC set) for entering slave receiver or transmitter
modes.
Set in master and slave receiver modes, to force an acknowledge (low level on
SDA).
This bit has no effect when in master transmitter mode.
1CR1
Control Rate bit 1
See Table 65.
0CR0
Control Rate bit 0
See Table 65.
Table 72. SSDAT (095h) - Syncrhonous Serial Data register (read/write)
SD7SD6SD5SD4SD3SD2SD1SD0
76543210
Bit
Number
Bit
Mnemonic Description
7 SD7 Address bit 7 or Data bit 7.
6 SD6 Address bit 6 or Data bit 6.
5 SD5 Address bit 5 or Data bit 5.
4 SD4 Address bit 4 or Data bit 4.
3 SD3 Address bit 3 or Data bit 3.
2 SD2 Address bit 2 or Data bit 2.