Datasheet
Table Of Contents
- Features
- Description
- Block Diagram
- SFR Mapping
- Pin Configurations
- Oscillators
- Enhanced Features
- Dual Data Pointer Register DPTR
- Expanded RAM (XRAM)
- Reset
- Power Monitor
- Timer 2
- Programmable Counter Array PCA
- Serial I/O Port
- Interrupt System
- Power Management
- Keyboard Interface
- 2-wire Interface (TWI)
- Serial Port Interface (SPI)
- Hardware Watchdog Timer
- ONCE(TM) Mode (ON Chip Emulation)
- Power-off Flag
- EEPROM Data Memory
- Reduced EMI Mode
- Flash Memory
- Electrical Characteristics
- Absolute Maximum Ratings
- DC Parameters
- AC Parameters
- Explanation of the AC Symbols
- External Program Memory Characteristics
- External Program Memory Read Cycle
- External Data Memory Characteristics
- External Data Memory Write Cycle
- External Data Memory Read Cycle
- Serial Port Timing - Shift Register Mode
- Shift Register Timing Waveforms
- External Clock Drive Waveforms
- AC Testing Input/Output Waveforms
- Float Waveforms
- Clock Waveforms
- Ordering Information
- Packaging Information
- Table of Contents
94
AT89C51ID2
4289C–8051–11/05
Table 70. Miscellaneous Status
C0h
Data byte in SSDAT has been
transmitted; NOT ACK has
been received
No SSDAT action or
No SSDAT action or
No SSDAT action or
No SSDAT action
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START
condition will be transmitted when the bus
becomes free
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1. A START condition will be transmitted
when the bus becomes free
C8h
Last data byte in SSDAT has
been transmitted (AA=0); ACK
has been received
No SSDAT action or
No SSDAT action or
No SSDAT action or
No SSDAT action
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START
condition will be transmitted when the bus
becomes free
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1. A START condition will be transmitted
when the bus becomes free
Table 69. Status in Slave Transmitter Mode (Continued)
Status
Code
(SSCS)
Status of the 2-wire bus and
2-wire hardware
Application Software Response
Next Action Taken By 2-wire Software
To/from SSDAT To SSCON
STA STO SI AA
Status
Code
(SSCS)
Status of the 2-wire
bus and 2-wire
hardware
Application Software Response
Next Action Taken By 2-wire
Software
To/from
SSDAT
To SSCON
STA STO SI AA
F8h
No relevant state
information
available; SI= 0
No SSDAT
action
No SSCON action Wait or proceed current transfer
00h
Bus error due to an
illegal START or
STOP condition
No SSDAT
action
010X
Only the internal hardware is
affected, no STOP condition is
sent on the bus. In all cases,
the bus is released and STO is
reset.