Datasheet
Table Of Contents
- Features
- Description
- Block Diagram
- SFR Mapping
- Pin Configurations
- Oscillators
- Enhanced Features
- Dual Data Pointer Register DPTR
- Expanded RAM (XRAM)
- Reset
- Power Monitor
- Timer 2
- Programmable Counter Array PCA
- Serial I/O Port
- Interrupt System
- Power Management
- Keyboard Interface
- 2-wire Interface (TWI)
- Serial Port Interface (SPI)
- Hardware Watchdog Timer
- ONCE(TM) Mode (ON Chip Emulation)
- Power-off Flag
- EEPROM Data Memory
- Reduced EMI Mode
- Flash Memory
- Electrical Characteristics
- Absolute Maximum Ratings
- DC Parameters
- AC Parameters
- Explanation of the AC Symbols
- External Program Memory Characteristics
- External Program Memory Read Cycle
- External Data Memory Characteristics
- External Data Memory Write Cycle
- External Data Memory Read Cycle
- Serial Port Timing - Shift Register Mode
- Shift Register Timing Waveforms
- External Clock Drive Waveforms
- AC Testing Input/Output Waveforms
- Float Waveforms
- Clock Waveforms
- Ordering Information
- Packaging Information
- Table of Contents
81
AT89C51ID2
4289C–8051–11/05
Figure 30. Block Diagram
Address Register
Comparator
Timing &
Control
logic
Arbitration &
Sink Logic
Serial clock
generator
Shift Register
Control Register
Status Register
Status
Decoder
Input
Filter
Output
Stage
Input
Filter
Output
Stage
ACK
Status
Bits
8
8
7
8
Internal Bus
Timer 1
overflow
F
CLK PERIPH
/4
Interrupt
SDA
SCL
SSADR
SSCON
SSDAT
SSCS
PI2.1
PI2.0