Datasheet
Table Of Contents
- Features
- Description
- Block Diagram
- SFR Mapping
- Pin Configurations
- Oscillators
- Enhanced Features
- Dual Data Pointer Register DPTR
- Expanded RAM (XRAM)
- Reset
- Power Monitor
- Timer 2
- Programmable Counter Array PCA
- Serial I/O Port
- Interrupt System
- Power Management
- Keyboard Interface
- 2-wire Interface (TWI)
- Serial Port Interface (SPI)
- Hardware Watchdog Timer
- ONCE(TM) Mode (ON Chip Emulation)
- Power-off Flag
- EEPROM Data Memory
- Reduced EMI Mode
- Flash Memory
- Electrical Characteristics
- Absolute Maximum Ratings
- DC Parameters
- AC Parameters
- Explanation of the AC Symbols
- External Program Memory Characteristics
- External Program Memory Read Cycle
- External Data Memory Characteristics
- External Data Memory Write Cycle
- External Data Memory Read Cycle
- Serial Port Timing - Shift Register Mode
- Shift Register Timing Waveforms
- External Clock Drive Waveforms
- AC Testing Input/Output Waveforms
- Float Waveforms
- Clock Waveforms
- Ordering Information
- Packaging Information
- Table of Contents
75
AT89C51ID2
4289C–8051–11/05
Registers Table 58. PCON Register
PCON (S87:h) Power configuration Register
Reset Value= XXXX 0000b
76543210
---POFGF1GF0PD IDL
Bit
Number
Bit
Mnemonic Description
7-5 -
Reserved
The value read from these bits is indeterminate. Do not set these bits.
4POF
Power-Off Flag
Cleared to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set
by software.
3GF1
General Purpose flag 1
One use is to indicate whether an interrupt occurred during normal operation or
during Idle mode.
2GF0
General Purpose flag 0
One use is to indicate whether an interrupt occurred during normal operation or
during Idle mode.
1PD
Power-Down Mode bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Power-Down mode.
If IDL and PD are both set, PD takes precedence.
0IDL
Idle Mode bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Idle mode.
If IDL and PD are both set, PD takes precedence.