Datasheet
Table Of Contents
- Features
- Description
- Block Diagram
- SFR Mapping
- Pin Configurations
- Oscillators
- Enhanced Features
- Dual Data Pointer Register DPTR
- Expanded RAM (XRAM)
- Reset
- Power Monitor
- Timer 2
- Programmable Counter Array PCA
- Serial I/O Port
- Interrupt System
- Power Management
- Keyboard Interface
- 2-wire Interface (TWI)
- Serial Port Interface (SPI)
- Hardware Watchdog Timer
- ONCE(TM) Mode (ON Chip Emulation)
- Power-off Flag
- EEPROM Data Memory
- Reduced EMI Mode
- Flash Memory
- Electrical Characteristics
- Absolute Maximum Ratings
- DC Parameters
- AC Parameters
- Explanation of the AC Symbols
- External Program Memory Characteristics
- External Program Memory Read Cycle
- External Data Memory Characteristics
- External Data Memory Write Cycle
- External Data Memory Read Cycle
- Serial Port Timing - Shift Register Mode
- Shift Register Timing Waveforms
- External Clock Drive Waveforms
- AC Testing Input/Output Waveforms
- Float Waveforms
- Clock Waveforms
- Ordering Information
- Packaging Information
- Table of Contents
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AT89C51ID2
4289C–8051–11/05
Table 52. IEN1 Register
IEN1 - Interrupt Enable Register (B1h)
Reset Value = XXXX X000b
Bit addressable
76543210
- - - - - ESPI ETWI EKBD
Bit
Number
Bit
Mnemonic Description
7-Reserved
6-Reserved
5-Reserved
4-Reserved
3-Reserved
2 ESPI
SPI interrupt Enable bit
Cleared to disable SPI interrupt.
Set to enable SPI interrupt.
1ETWI
TWI interrupt Enable bit
Cleared to disable TWI interrupt.
Set to enable TWI interrupt.
0 EKBD
Keyboard interrupt Enable bit
Cleared to disable keyboard interrupt.
Set to enable keyboard interrupt.