Datasheet
Table Of Contents
- Features
- Description
- Block Diagram
- SFR Mapping
- Pin Configurations
- Oscillators
- Enhanced Features
- Dual Data Pointer Register DPTR
- Expanded RAM (XRAM)
- Reset
- Power Monitor
- Timer 2
- Programmable Counter Array PCA
- Serial I/O Port
- Interrupt System
- Power Management
- Keyboard Interface
- 2-wire Interface (TWI)
- Serial Port Interface (SPI)
- Hardware Watchdog Timer
- ONCE(TM) Mode (ON Chip Emulation)
- Power-off Flag
- EEPROM Data Memory
- Reduced EMI Mode
- Flash Memory
- Electrical Characteristics
- Absolute Maximum Ratings
- DC Parameters
- AC Parameters
- Explanation of the AC Symbols
- External Program Memory Characteristics
- External Program Memory Read Cycle
- External Data Memory Characteristics
- External Data Memory Write Cycle
- External Data Memory Read Cycle
- Serial Port Timing - Shift Register Mode
- Shift Register Timing Waveforms
- External Clock Drive Waveforms
- AC Testing Input/Output Waveforms
- Float Waveforms
- Clock Waveforms
- Ordering Information
- Packaging Information
- Table of Contents
66
AT89C51ID2
4289C–8051–11/05
Table 50. IPL0 Register
IPL0 - Interrupt Priority Register (B8h)
Reset Value = X000 0000b
Bit addressable
76543210
- PPCL PT2L PSL PT1L PX1L PT0L PX0L
Bit
Number
Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 PPCL
PCA interrupt Priority bit
Refer to PPCH for priority level.
5PT2L
Timer 2 overflow interrupt Priority bit
Refer to PT2H for priority level.
4 PSL
Serial port Priority bit
Refer to PSH for priority level.
3PT1L
Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority level.
2 PX1L
External interrupt 1 Priority bit
Refer to PX1H for priority level.
1PT0L
Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
0 PX0L
External interrupt 0 Priority bit
Refer to PX0H for priority level.