Datasheet
Table Of Contents
- Features
- Description
- Block Diagram
- SFR Mapping
- Pin Configurations
- Oscillators
- Enhanced Features
- Dual Data Pointer Register DPTR
- Expanded RAM (XRAM)
- Reset
- Power Monitor
- Timer 2
- Programmable Counter Array PCA
- Serial I/O Port
- Interrupt System
- Power Management
- Keyboard Interface
- 2-wire Interface (TWI)
- Serial Port Interface (SPI)
- Hardware Watchdog Timer
- ONCE(TM) Mode (ON Chip Emulation)
- Power-off Flag
- EEPROM Data Memory
- Reduced EMI Mode
- Flash Memory
- Electrical Characteristics
- Absolute Maximum Ratings
- DC Parameters
- AC Parameters
- Explanation of the AC Symbols
- External Program Memory Characteristics
- External Program Memory Read Cycle
- External Data Memory Characteristics
- External Data Memory Write Cycle
- External Data Memory Read Cycle
- Serial Port Timing - Shift Register Mode
- Shift Register Timing Waveforms
- External Clock Drive Waveforms
- AC Testing Input/Output Waveforms
- Float Waveforms
- Clock Waveforms
- Ordering Information
- Packaging Information
- Table of Contents
58
AT89C51ID2
4289C–8051–11/05
Table 39. Example of Computed Value When X2=1, SMOD1=1, SPD=1
Table 40. Example of Computed Value When X2=0, SMOD1=0, SPD=0
The baud rate generator can be used for mode 1 or 3 (refer to Figure 23.), but also for
mode 0 for UART, thanks to the bit SRC located in BDRCON register (Table 47.)
UART Registers Table 41. SADEN Register
SADEN - Slave Address Mask Register for UART (B9h)
Reset Value = 0000 0000b
Table 42. SADDR Register
SADDR - Slave Address Register for UART (A9h)
Reset Value = 0000 0000b
Baud Rates F
OSC
= 16. 384 MHz F
OSC
= 24MHz
BRL Error (%) BRL Error (%)
115200 247 1.23 243 0.16
57600 238 1.23 230 0.16
38400 229 1.23 217 0.16
28800 220 1.23 204 0.16
19200 203 0.63 178 0.16
9600 149 0.31 100 0.16
4800 43 1.23 - -
Baud Rates F
OSC
= 16. 384 MHz F
OSC
= 24MHz
BRL Error (%) BRL Error (%)
4800 247 1.23 243 0.16
2400 238 1.23 230 0.16
1200 220 1.23 202 3.55
600 185 0.16 152 0.16
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